Cisco Technology, Inc.

Tamba Networks, Inc.

Valo, Inc.

Juniper Networks, Inc.

Soren Pedersen

Barry W Field

Danny Thom

Kenneth M Buckland

Riccardo G Dorbolo

Thomas A Potter

Earl B Manchester

Radimir Shilshtut

Sina Soltani

Jan C Hobbel

Nad Karim

Rony Kurniawan

Charles R Dyer

Kenneth Huang

Ruturaj Pathak

Harsha Narayan

Robert D Howson, Jr

Lauren Trevor May

Tom Potter

Manish Lohani

Disclosed are a method, non-transitory medium, and system of a tunable design of an Interlaken region of an integrated circuit (IC). In one embodiment, a method comprises modeling a design abstraction of an Interlaken sub-circuit of an integrated circuit as a register transfer level (RTL) code within a data processing device, wherein a first stage of sequential logic in the RTL code is associated with a first stage of combinational logic in the RTL code. The method further comprises implementing, through a processor and based on a timing parameter input into a synthesis tool associated with the RTL code, a selective bypass or a selective enablement of the first stage of sequential logic. Still further, the method comprises synthesizing, through the processor, a netlist from the RTL code, wherein the first stage of sequential logic is sequentially bypassed or sequentially enabled.

Tunable design of an interlaken region of an integrated circuit

Disclosed are a method, non-transitory medium, and system of a tunable design of an Ethernet region of an integrated circuit (IC). In one embodiment, a method comprises modeling a design abstraction of an Ethernet sub-circuit of an integrated circuit as a register transfer level (RTL) code within a data processing device, wherein a first stage of sequential logic in the RTL code is associated with a first stage of combinational logic in the RTL code. The method further comprises implementing, through a processor and based on a timing parameter input into a synthesis tool associated with the RTL code, a selective bypass or a selective enablement of the first stage of sequential logic. Still further, the method comprises synthesizing, through the processor, a netlist from the RTL code, wherein the first stage of sequential logic is sequentially bypassed or sequentially enabled.

Tunable design of an ethernet region of an integrated circuit

A method may include counting the number of times each of a plurality of entries in a content addressable memory (CAM) matches one or more searches; grouping entries in the CAM into a first subset and a second subset based on the number of times each of the plurality of entries in the CAM matches one or more searches; and searching the first subset for a matching entry and, if no matching entry is found, searching the second subset for the matching entry.

Reducing content addressable memory (CAM) power consumption counters

Methods, apparatuses and systems facilitating the aggregation or bonding of communications paths into a higher-bandwidth, logical communications path. Embodiments of the present invention can be applied to bond different physical links (e.g., xDSL over twisted pairs), different channels on the same physical line, or even different channels or frequencies in a wireless communications network. The present invention further provides methods, apparatuses and systems facilitating the re-sequencing of data flows transmitted across bonded communications paths. In one embodiment, the re-sequencing methodology of the present invention adapts to the transmission delays (both absolute and relative) across the bonded communications path.

Methods, apparatuses and systems facilitating data transmission across bonded communications paths

Methods, apparatuses and systems facilitating the aggregation or bonding of physical communications links into higher-bandwidth logical links. A novel link bonding and encapsulation protocol scheme that optimizes the efficiency of data transfer across the physical links, while still allowing for desired Quality of Service (QoS) levels to high-priority traffic, such as voice data, with low delay requirements. Data streams are divided and concurrently transported over multiple physical links that are aggregated or bonded together to form one logical link. At the receive end, the original cell streams are recovered from the bonded logical links. In one embodiment, the physical links are xDSL links transmitting and receiving signals via conventional copper twisted-pair cabling. In one embodiment, the present invention allows telecommunications service providers to leverage their investments in existing twisted pair connection technologies to deliver high-bandwidth services to customers in a fast and cost-efficient manner.

Methods, apparatuses and systems facilitating aggregation of physical links into logical link

A rate adjustable backplane includes a set of switch slots configured to receive one or more switch cards forming a switch core and a plurality of line slots each configured to receive a line card. A low speed bus couples the line slots to the set of switch slots. A high speed bus also couples the line slots to the set of switch slots. Each line slot includes a low speed connector coupled to the low speed bus and a high speed connector coupled to the high speed bus. The low speed connector is adapted to receive a mating connector of a line card to establish a low speed communication connection between the line card and the switch core. The high speed connector is adapted to receive a mating connector of the line card to establish a high speed link between the line card and the switch core.

Rate adjustable backplane and method for a telecommunications node

A method and system for distributed processing of traffic in a telecommunications node includes receiving a traffic stream at a line card of the telecommunications node. The traffic stream includes a plurality of discrete cells. The cells are forwarded from the line card to a centralized switch of the telecommunications node. The centralized switch identifies cells that are of a particular type. Cells of the particular type are returned from the centralized switch to the line card. The returned cells are processed at the line card.

Method and system for distributed processing of traffic in a telecommunications node

A bus for a telecommunications node includes a frame repeating at a defined interval and including a defined number of slots. Each slot includes an overhead portion identifying a type of traffic in the slot and a service traffic portion transporting traffic of the type. A first slot in at least one frame transports in the service traffic portion asynchronous traffic and routing information for the asynchronous traffic in the telecommunications node. A second slot in the frame transports synchronous traffic in the service traffic portion and has a location in the frame associated with routing information for the synchronous traffic in the telecommunications node.

Method and system for transporting synchronous and asynchronous traffic on a bus of a telecommunications node

A switch card for telecommunications node includes a shared memory operable to store traffic channels. A time slot interchanger (TSI) is coupled to a first bus and to the shared memory. The TSI is operable based on predefined switching instructions to access the shared memory to stored traffic channels received from the first bus and to retrieve traffic channels for transmission on the first bus. An asynchronous transfer mode (ATM) switch is operable to switch a traffic cell based on header information in the traffic cell. A traffic converter is operable to convert traffic channels retrieved from the shared memory to traffic cells for processing by a bus fuser and to convert traffic cells to traffic channels for storage in the shared memory. The bus fuser is coupled to the shared memory through the traffic converter, the ATM switch, and a second bus. The bus fuser is operable to receive a traffic cell from each one of the traffic converter, the ATM switch, and the second bus and to route the traffic cell to another one of the traffic converter, the ATM switch, and the second bus.

Growing community of inventors

Petaluma, CA, United States of America

Soren Pedersen