Taiwan Semiconductor Manufacturing Comp. Ltd.

Sophia Wang

Heng-Hsin Liu

Hsien-Wei Chen

Chun-Hung Lin

Yung-Yao Lee

Chi-Yuan Shih

Ming-Yen Chiu

Fei-Gwo Tsai

Heng-Jen Lee

Yu-Chyi Harn

A method of determining overlay error. The method includes transferring a pattern from a reticle to a wafer and selecting a first set of data points to measure the positional difference between features on the reticle and features on the wafer. The method also includes determining a second set of data points characteristic of the first set of data points but containing fewer data points. A control system for using the second set of data points to dynamically adjust the position of the reticle.

Method of determining overlay error and control system for dynamic control of reticle position

A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.

Structure for integrated circuit alignment

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.

Structure of stacking scatterometry based overlay marks for marks footprint reduction

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Xin-Zhu, Taiwan

Sophia Wang