Samsung Electronics Co., Ltd.

Sooyong Lee

Jeeyong Lee

Seunghune Yang

Dongho Kim

Jaeho Jeong

Bong-Soo Kang

Bongsoo Kang

Sangwook Kim

Sangtae Kim

Mincheol Kang

Jae Hyun Choi

Kyungjae Park

Kang-Min Jung

Kyoil Koo

Cheol Ryou

Jungmin Kim

Seorim Moon

Changmook Yim

Yangwoo Heo

Mi-Jin Kwon

Jaeseong Yoon

Hyeyoung Ji

A memory device may include a memory cell array including first to fourth memory cells respectively connected to first to fourth word lines, a sense amplifier including a first sensing circuit that is configured to generate a first weighted sum based on a first weight stored in the first memory cell and a second weight stored in the third memory cell, in response to an activation of the first and third word lines at a first time point, an input and output circuit that is configured to output the first weighted sum to an external device in response to a first read command, and a restore circuit that is configured to perform a restore operation for storing a first data item stored in the second memory cell to the first memory cell and for storing a second data item stored in the fourth memory cell to the third memory cell after the first time point.

Memory device and operation method thereof

A method for manufacturing a semiconductor device, includes receiving a first layout including patterns for the manufacturing of the semiconductor device, generating a second layout by performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout, generating a third layout by performing optical proximity correction (OPC) on the second layout, and performing a multiple patterning process based on the third layout. The multiple patterning process includes patterning first-type patterns, and patterning second-type patterns. The machine learning-based process proximity correction is performed based on features of the first-type patterns and features of the second-type patterns.

Method and computing device for manufacturing semiconductor device

Disclosed is a method for fabricating of a semiconductor device. The method includes receiving a first layout including patterns for the fabrication of the semiconductor device, performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout to generate a second layout, and performing optical proximity correction (OPC) on the second layout to generate a third layout.

With respect to each layout pattern of a plurality of layout patterns included in a layout for semiconductor processes, where the layout includes schematic information to form process patterns of a semiconductor device, vertical features indicating an effect of a lower structure on the process patterns are determined, and the lower structure indicates a structure that is formed in the semiconductor device before the process patterns are formed. A machine learning module is trained based on a training layout and the vertical features of the training layout. A design layout with schematic information to form target process patterns is corrected based on the trained machine learning module, the design layout and the vertical features of the design layout. Reliability and integration of the layout for the semiconductor processes may be increased by correcting the layout based on the vertical features and the horizontal features.

Methods and devices of correcting layout for semiconductor processes using machine learning

A method of fabricating a semiconductor device includes performing an optical proximity correction (OPC) operation on a design pattern of a layout, and forming a photoresist pattern on a substrate, using a photomask which is manufactured with the layout corrected by the OPC operation. The OPC operation includes generating a target pattern based on the design pattern, performing a first OPC operation, based on the target pattern, to generate a first correction pattern, measuring a target error by comparing a first simulation image of the first correction pattern with the target pattern, generating a retarget pattern from the target pattern, based on the target error, and performing a second OPC operation, based on the retarget pattern, to generate a second correction pattern.

Optical proximity correction method and method of fabricating a semiconductor device using the same

Disclosed is an operating method of an electronic device which includes receiving a design layout for manufacturing the semiconductor device, generating a first layout by performing machine learning-based process proximity correction (PPC), generating a second layout by performing optical proximity correction (OPC), and outputting the second layout for a semiconductor process. The generating of the first layout includes generating a first after cleaning inspection (ACI) layout by executing a machine learning-based process proximity correction module on the design layout, generating a second after cleaning inspection layout by adjusting the design layout based on a difference of the first after cleaning inspection layout and the design layout and executing the process proximity correction module on the adjusted layout, and outputting the adjusted layout as the first layout, when a difference between the second after cleaning inspection layout and the design layout is smaller than or equal to a threshold value.

Electronic device for manufacturing semiconductor device and operating method of electronic device

A semiconductor device includes a peripheral circuit region including a first substrate and circuit devices on the first substrate, a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer, and a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region in the first direction.

Semiconductor device including dummy channels and through wiring structure

A method of manufacturing a semiconductor device includes forming a lower mold having lower layers stacked on a substrate and lower channel structures passing therethrough; forming an upper mold including upper layers stacked on the lower mold and upper channel structures passing therethrough; removing the upper mold to expose an upper surface of the lower mold; separating an upper original image in which traces of the upper channel structures are displayed, and a lower original image in which the lower channel structures are displayed, from an original image capturing the upper surface of the lower mold; inputting the upper original image into a learned neural network to acquire an upper restored image in which cross sections of the upper channel structures are displayed; and comparing the upper restored image with the lower original image to verify an alignment state of the upper and lower molds.

Manufacturing method of semiconductor device

A method of fabricating a semiconductor device includes designing a layout, forming a photomask based on the layout, correcting an optical transmittance of the photomask, and performing a photolithography process using the photomask having the corrected optical transmittance to form a pattern on a substrate. The correcting the optical transmittance of the photomask includes creating an intensity map by capturing light that passes through the photomask, simulating the layout to create a virtual intensity map, and correcting an optical transmittance of a mask substrate of the photomask based on the intensity map and the virtual intensity map.

Method of fabricating a semiconductor device

An electronic device is provided which includes a plurality of displays, a processor electrically connected to the plurality of displays, and a memory electrically connected to the processor, in which the memory stores a middleware, which when executed by a processor divides image data to be displayed on the plurality of displays, and transmits the divided image data to display drivers of the plurality of displays.

Growing community of inventors

Yongin-si, South Korea

Sooyong Lee