Netlist, Inc.

Soonju Choi

Hyun K Lee

Jayesh R Bhakta

A memory module comprises memory devices, a data module and a control module. The memory module is operable in a first mode in which at least some of the memory devices are accessed by a system memory controller in a computer system for memory read and/or write operations at a memory access speed, the control module is configured to register address and control signals associated with the memory read and/or write operations, and the data module is configured to propagate data signals between the at least some of the memory devices and the memory controller. The memory module is further operable in a second mode in which the memory devices are not accessed by the system memory controller for memory read or write operations, and the data module is configured to communicate data signals with at least some of the memory devices at the memory access speed.

Multi-mode memory subsystem including control and data modules for buffering and testing

A memory module is operable in a computer system to communicate data with a system memory controller via a system memory bus. The memory module comprises a plurality of memory devices mounted on a circuit board, a data module mounted on the circuit board and coupled between the plurality of memory devices and the system memory bus, and a control circuit mounted on the circuit board and coupled to the data module, the plurality of memory devices, and the system memory bus. The data module includes a plurality of data handlers in a plurality of integrated circuits. The memory module is operable in any of a plurality of modes, including a first mode and a second mode. The plurality of memory devices in the first mode is accessed by the system memory controller for normal memory read or write operations. The plurality of memory devices in the second mode communicate data signals with the data module while the memory module is not being accessed by the system memory controller for normal memory read or write operations.

Multi mode memory module with data handlers

A memory subsystem is operable with a system memory controller. The memory subsystem comprises memory devices mounted on a circuit board, a data module mounted on the circuit board; and a control module mounted on the circuit board to provide address and control signals to the memory devices. The memory subsystem is operable in any of a plurality of modes including a normal mode and a test mode. During the normal mode, the control module provides the address and control signals based on address and control signals from the system memory controller, and the data module enables data paths between the memory devices and the system memory controller. During the test mode, the control module generates the address and control signals, and the data module isolates the memory devices from the system memory controller.

Multi-mode memory module with data handlers

A memory module for operating with a system memory controller comprises a plurality of data ports, a plurality of memory devices organized in ranks, and a plurality of data handlers. Each respective data handler is coupled to a respective set of data ports of the plurality of data ports and to a respective set of memory devices of the plurality of memory devices. Each set of memory devices include at least one memory device from each rank. In a normal mode, each respective data handler is configured to provide write data received from the system memory controller via the respective data ports to the respective set of memory devices. In a test mode, each respective data handler is configured to provide test data generated in the respective data handler to the respective set of memory devices.

Apparatus and method for self-test in a multi-rank memory module

A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devices comprising data, address, and control ports. The memory module also includes a control module configured to generate address and control signals for testing the memory devices. The memory module includes a data module comprising a plurality of data handlers. Each data handler is operable independently from each of the other data handlers of the plurality of data handlers. Each data handler is operatively coupled to a corresponding plurality of the data ports of one or more of the memory devices and is configured to generate data for writing to the corresponding plurality of data ports.

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Irvine, CA, United States of America

Soonju Choi