Skhynix Inc.

Korea Advanced Institute of Science and Technology

Soon-Young Kang

Dae-Sung Kim

Jaekyun Moon

Sung-Whan Yoon

Bo-Seok Jeong

A semiconductor memory system includes: a semiconductor memory device to store a codeword; and a low-density parity check (LDPC) decoder to decode the codeword, based on a parity check matrix, to generate a decoded codeword, wherein the LDPC decoder includes: a selector to select one or more sub-matrices that share the same layer index of the parity check matrix, and select variable nodes corresponding to columns included in the selected one or more sub-matrices based on a threshold value and a number of unsatisfied check nodes (UCNs) connected to the selected variable nodes; a variable node updater to update decision values of variable nodes corresponding to all columns included in the parity check matrix; a syndrome checker to determine whether decoding the codeword has been performed successfully or not; and a check node updater to update a backup syndrome, the threshold value, and a size of a processing unit.

LDPC decoder, semiconductor memory system, and operating method thereof

A controller may include a first encoder suitable for generating a first polar parity by performing a first polar encoding operation to respective first sections of an original message having a plurality of symbols, an interleaver suitable for generating an interleaved message by interleaving the original message according to first reliabilities, which are predetermined depending on locations of the respective symbols in the respective first sections in the original message, and second reliabilities, which are predetermined depending on locations of the respective symbols in the interleaved message, a second encoder suitable for generating a second polar parity by performing a second polar encoding operation to respective second sections included in the interleaved message and a memory interface suitable for storing the original message, the first polar parity and the second polar parity into a memory.

Controller and operating method thereof

A controller including: an initialization unit initializing values and states of variable nodes and initializing values of check nodes; a variable node update unit updating the values and states of the variable nodes; a check node update unit updating the values of the check nodes based on the updated values and states of the variable nodes; and a syndrome check unit deciding iteration of the operation of the variable node update unit and the check node update unit when the values of the check nodes are not all in a satisfied state, the variable node update unit calculates reliability values of the variable nodes and a reference flip value based on a result of a previous iteration, and the variable node update unit updates the values and states of the variable nodes based on the reference flip value and the reliability values and states of the variable nodes.

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Yongin-si, South Korea

Soon-Young Kang