Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

International Business Machines Corporation

Globalfoundries Inc.

Renesas Electronics Corporation

Enesas Electronics Corporation

Soon Yoeng Tan

Sia Kim Tan

Huey Ming Chong

Qun Ying Lin

Paul Willard Ackmann

Teck Jung Tang

Liang Choo Hsia

Guoxiang Ning

Andreas Knorr

Ian D Melville

Liang-Choo Hsia

Yasushi Yamagata

Gek Soon Chua

Arthur Hotzel

Qunying Lin

Guo Xiang Ning

Byoung-Il Choi

Soo Muay Goh

Yelei Vianna Yao

Scott C Johnson

Frank Scott Johnson

Byoung Il Choi

Seok Yan Poh

Ngar Chen Stella Lau

Srinidhi Ramamoorthy

Angeline Ho

Angeline Ho Chye Ee

Hendry Renaldo

Hui Leang Ong

Jason Phua

Hury Ming Chong

Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.

Multi-project wafer with IP protection by reticle mask pattern modification

Methods for reducing reticle transmission differences and for optimizing layer placement for overlay in MTRs and CTRs are disclosed. Embodiments include providing a reticle having a prime area and a frame area surrounding the prime area; determining RT differences across the prime area; and providing RT adjustment structures on the reticle to decrease the RT differences. Other embodiments include grouping multiple layers of a semiconductor production flow, the layers for each group having an RT difference less than a predetermined value; and placing the layers on plural ordered reticles of a reticle set, each reticle having multiple image fields, by selecting, for each reticle, layers from a single group and optimizing placement of the layers for overlay. Other embodiments include selectively rotating image fields on a reticle having multiple image fields to improve overlay, or optimizing placement of DDLs on CTRs by placing each design orientation on a different reticle.

Cross technology reticle (CTR) or multi-layer reticle (MLR) CDU, registration, and overlay techniques

A pellicle is provided for use with a lithographic photomask during manufacture of semiconductor devices, printed circuit boards, liquid crystal displays, etc. The pellicle has a pellicle frame comprising four pellicle walls that define a trapezoidal area sized and shaped to correspond to a pattern area of a lithographic photomask; and a pellicle film extending across the trapezoidal area and affixed to a film-side edge of the pellicle frame; wherein any one of the four pellicle walls has a vent hole therethrough, the vent hole being located proximate a corner of the frame and if matter passes through the vent hole, the foreign matter will not obstruct the pattern area during use of the lithographic photomask.

Pellicles and devices comprising a photomask and the pellicle

Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits are provided. In one embodiment, a method for converting a planar integrated circuit design to a non-planar integrated circuit design includes identifying a rectangular silicon active area in the planar integrated circuit design, superimposing a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines, and generating a rectangular active silicon marker area encompassing the silicon active area. Furthermore, the method includes generating fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area, and removing the fin mandrels from areas of the design grid outside of the active silicon marker area.

Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits

Semiconductor wafers employing a fixed coordinate metrology scheme and methods for fabricating integrated circuits using the same are disclosed. In an exemplary embodiment, a semiconductor wafer employing a fixed-coordinate metrology scheme includes an external scribe region in the form of a first rectangular ring, the first rectangular ring defining a first interior space inward from the external scribe region and an interior scribe region in the form of a second rectangular ring, disposed within the first interior space and immediately adjacent to the external scribe region at all points along its exterior perimeter, the second rectangular ring defining a second interior space inward from the interior scribe region, the second interior space being wholly within the first interior space. The semiconductor wafer further includes a technology-specific tile region disposed within the second interior space and immediately adjacent to the interior scribe region and an electrical testable scribe line measurement (ETSLM) region disposed within the second interior space and immediately adjacent to both the technology-specific tile region and the interior scribe region. Still further, the semiconductor wafer includes a free floorplan area disposed within the second interior space and immediately adjacent to both the ETSLM region and the interior scribe region.

Semiconductor wafers employing a fixed-coordinate metrology scheme and methods for fabricating integrated circuits using the same

Methods for forming an alignment mark and the resulting mark are disclosed. Embodiments may include forming a first shape having rotational symmetry; forming a second shape; and forming an alignment mark by combining the first shape and one or more of the second shape, wherein the alignment mark has rotational symmetry.

Forming alignment mark and resulting mark

IP protection

A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.

Integrated circuit system with sub-geometry removal and method of manufacture thereof

An approach for providing conversion of a planar design to a FinFET design is disclosed. Embodiments include: receiving a planar design having a plurality of diffusion regions; overlapping a plurality of parallel fin mandrels with a plurality of evenly-spaced parallel lines of a grid; snapping the diffusion regions to the grid based on the parallel lines; and generating a FinFET design based on the overlapping and the snapping. Embodiments include the parallel lines and the parallel fin mandrels being perpendicular to a poly orientation associated with the planar design, and determining a spacing length between the parallel lines; determining a plurality of edges of the diffusion regions that are parallel to the poly orientation; and cropping the diffusion regions until each of the edges has a length that is a multiple of the spacing length.

Providing conversion of a planar design to a FinFET design

A method of manufacture an integrated circuit system includes: forming an insulation region in a base layer; filling an insulator in the insulation region around a perimeter of a main chip region; forming a contact directly on and within planar extents of the insulator; and forming an upper layer over the contact to protect the main chip region.

Integrated circuit system with sealring and method of manufacture thereof

A method of making a mask is disclosed. The method includes providing a first and a second mask layers and disposing a first phase shift region on the first mask layer. A second phase shift region is disposed on the second mask layer, wherein the first and second phase shift regions are out of phase. A continuous unit cell is formed in the first phase shift region. The unit cell comprises a center section and distinct extension sections. The extension sections are contiguous to and extend outwards from the center section. The distinct extension sections have a same width as the center section. The second phase shift region is adjacent to the unit cell in the first phase shift region.

Mask and method to pattern chromeless phase lithography contact hole

A method and structure for removing side lobes is provided by positioning first and second radiation transparent regions of respective first and second phases at a first plane with the first and second phases being substantially out of phase. Further, positioning the first and the second region to cause radiation at a second plane to be neutralized in a first region, not to be neutralized in a second region, and to have a side lobe in a third region. Further, positioning a non-transparent region at the first plane to assure radiation at the second plane to be neutralized in the first region and positioning a third radiation transparent region of the first or second phase at the first plane to neutralize the side lobes in the third region at the second plane.

Method and apparatus for removing radiation side lobes

A method of fabricating a device is presented. The method includes forming a mask that includes multiple images. A substrate is patterned using the mask. An image of the multiple images corresponds to a respective patterning process. The substrate is processed further to complete the processing of the substrate to form the desired function of the device.

Cross technology reticles

Growing community of inventors

Singapore, Singapore

Soon Yoeng Tan