Ncku Research and Development Foundation

Himax Technologies, Inc.

National Cheng-Kung University

Himax Media Solutions, Inc.

Novatek Microelectronics Corp.

Upbeat Technology Co., Ltd

Lncku Research and Development Foundation

Himas Media Solutions, Inc.

Soon-Jyh Chang

Chung-Ming Huang

Chih-Haur Huang

Jin-Fu Lin

Guan-Ying Huang

Yen-Long Lee

Chun-Cheng Liu

Wei-Li He

Kuen-Jong Lee

Chung-Ho Chen

Meng-Ju Chiang

Hao-Sheng Wu

Chien-Hung Tsai

Kuo-Chan Huang

Lih-Yih Chiou

Chia-Min Lin

Che-Wei Hsu

Po-Ying Chen

Liang-Ting Kuo

Chung-Chieh Chen

Chun-Po Huang

Shuo-Hong Hung

Che-Hsun Kuo

Yi-Lun Chiang

Wen-Yu Su

Yi-Shen Cheng

Ying-Zu Lin

Ming-Liang Chung

An-Sheng Chao

Wen-Chia Luo

Shih-Ming Luo

Chuo-Ming Kuo

Kai-Cheng Cheng

Chao-Hsien Ma

Peng-Yu Chen

Yen-Chi Chen

Chia-Chuan Lee

Chih-Hung Kuo

Tz-Jing Shau

Yu-Po Cheng

Jih-Ren Goh

Li-Jen Chang

Yen Long Lee

A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) comprises: a plurality of switch capacitor arrays, used to sample an analog input signal; a noise shaping circuit including a fourth-order CIFF (Cascade of Integrators with Feed-Forward) loop filter having two second-order cascaded CIFF loop filters, in the fourth-order CIFF loop filter, a first-order extraction capacitor and a second-order extraction capacitor sharing a first amplifier, and a third-order extraction capacitor and a fourth-order extraction capacitor sharing a second amplifier; a comparator for comparing a plurality of output signals from the noise shaping circuit to produce a plurality of comparison results; and a logic circuit for generating a digital output signal and controlling the switch capacitor arrays based on comparison results from the comparator.

High-order noise-shaping successive approximation register (SAR) analog-to-digital converter and method thereof

A static random-access memory (SRAM) cell includes a first inverter and a second inverter being cross-coupled; a first access transistor that accesses an output of the first inverter under control of a word line; a second access transistor that accesses an output of the second inverter under control of the word line; a first passage transistor that passes a common-mode voltage, controlled by the output of the first inverter; a second passage transistor that passes an input signal, controlled by the output of the second inverter; and a capacitor switchably coupled to receive the common-mode voltage and the input signal through the first passage transistor and the second passage transistor respectively.

Recognition system and SRAM cell thereof

An acoustic feature extraction (AFE) circuit includes a plurality of band-pass filters (BPFs) adaptable to a plurality of channels with different band-pass frequency ranges respectively for switchably receiving an amplified signal, thereby generating corresponding filtered signals, the plurality of BPFs including an operational amplifier that is shared among the plurality of channels; and a rectifier switchably coupled to receive the filtered signals, thereby generating a rectified signal. The amplified signal is time-division demultiplexed onto the BPFs in different phases, and the filtered signals are time-division multiplexed onto the rectifier in different phases.

Voice activity detection system and acoustic feature extraction circuit thereof

A single-ended successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) having a first capacitor associated with a most significant bit (MSB) of the output code, and a second capacitor associated with other bit or bits of the output code; and a second DAC having a first capacitor associated with a MSB of the output code, and a second capacitor associated with other bit or bits of the output code. A bottom plate of the first capacitor of the second DAC is connected to a negative reference voltage in all phases.

Single-ended successive approximation register analog-to-digital converter

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) coupled to receive a first input voltage to generate a first output voltage; a second DAC coupled to receive a second input voltage to generate a second output voltage; a comparator having a positive input node coupled to receive the first output voltage of the first DAC, and a negative input node coupled to receive the second output voltage of the second DAC; a SAR controller that controls switching of the first DAC and the second DAC according to a comparison output of the comparator, thereby generating an output code; a first calibration circuit coupled between the positive input node of the comparator and a ground voltage; and a second calibration circuit coupled between the negative input node of the comparator and the ground voltage.

Successive approximation register analog-to-digital converter

A successive approximation register (SAR) analog to digital converter (ADC) and a method of detecting an offset of a comparator are introduced. The SAR ADC includes a switch circuit, a comparator and a calibration circuit. The switch circuit is configured to perform a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal. The comparator is coupled to the switching circuit and is configured to compare the first intermediate analog signal and the second intermediate analog signal before the swapping operation to generate a least-significant-bit value. The comparator is further configured to compare the first swapped analog signal and the second swapped analog signal after the swapping operation to generate a calibration bit value. The calibration circuit is configured to determine whether the comparator has an offset according to the least-significant-bit value and the calibration bit value.

Successive approximation register analog to digital converter and offset detection method thereof

A reference ripple suppression circuit adaptable to a successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of code-dependent compensation cells, each including a logic circuit and a compensation capacitor. A first plate of the compensation capacitor is coupled to receive a reference voltage to be compensated, and a second plate of the compensation capacitor is coupled to receive an output of the logic circuit performing on an output code of the SAR ADC and at least one logic value representing a bottom-plate voltage of a switched digital-to-analog converter (DAC) of the SAR ADC. (k&#x2212;1) of the code-dependent compensation cells are required maximally for k-th switching of the SAR ADC.

SAR ADC and a reference ripple suppression circuit adaptable thereto

A successive approximation register (SAR) analog-to-digital converter (ADC) with high linearity for generating an n-bit converted output includes a first capacitor digital-to-analog (DAC) and a second capacitor DAC. One of the first capacitor DAC and the second capacitor DAC that has greater output signal is defined as a higher-voltage capacitor DAC, and the other as an un-switching capacitor DAC. In an m-th conversion phase, an (m&#x2212;1)-th capacitor of the un-switching capacitor DAC is switched according to a comparison between output signals of the higher-voltage capacitor DAC and the un-switching capacitor DAC.

SAR ADC with high linearity

An interfacing circuit adaptable to an analog-to-digital converter (ADC) includes a sample and hold (S/H) circuit; an input switch; an input capacitor with a first end connected to an input end of a comparator of the ADC via the S/H circuit, and with a second end connected to receive an input signal via the input switch; a hold switch connected between the second end of the input capacitor and an original common-mode voltage; a reset switch connected between the input end of the comparator and a target common-mode voltage; and a front switch connected between the first end of the input capacitor and the target common-mode voltage.

ADC and an interfacing circuit adaptable thereto

A system and a method for temperature sensing of three-dimensional integrated circuits are revealed. The three-dimensional integrated circuit is formed by stacking of a plurality of chip layers that execute specific functions. The chip layer includes a master layer and at least one slave layer. The master layer is disposed with a master temperature sensor while a first thermal conductive part is arranged at the slave layer where heat is detected. The first thermal conductive part and the master temperature sensor are connected by a thermal conductive structure. Thereby temperature of various points at different chip layers is conducted to the same chip layer by Through Silicon Vias to be measured and calibrated. The design complexity and the implementation cost of the temperature sensing system are significantly reduced.

System and method for temperature sensing of three-dimensional integrated circuit

A clock and data recovery (CDR) circuit is provided. A phase detection circuit receives an input signal and a clock signal to output a first voltage signal. A first comparing circuit determines whether the first voltage signal is within a voltage range to output a first up signal and a first down signal. A counting circuit updates a counting value according to the input signal and the clock signal. A second comparing circuit determines whether the counting value is within a value range to output a second up signal and a second down signal. A selection circuit outputs a second voltage signal according to the first up signal, the first down signal, the second up signal, and the second down signal. A voltage controlled oscillator outputs the clock signal according to the first voltage signal and the second voltage signal.

Clock and data recovery circuit with bidirectional frequency detection and electronic device using the same

A multi-point temperature sensing method for integrated circuit chips and a system of the same are revealed. The system includes at least one slave temperature sensor embedded at preset positions for measuring temperature of a block and a master temperature sensor embedded in an integrated circuit chip and electrically connected to each slave temperature sensor. Variations of the slave temperature sensor induced by variations of process, voltage and temperature are corrected by the master temperature sensor. Thus the area the temperature sensors required on the integrated circuit chip is dramatically reduced and the stability of the temperature control system is improved. The problem of conventional System-on-a-Chip that only a limited number of temperature sensors could be used due to the area they occupied can be solved.

Multi-point temperature sensing method for integrated circuit chip and system of the same

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Tainan, Taiwan

Soon-Jyh Chang