Samsung Electro-mechanics Co., Ltd.

Soon Gyu Yim

Seung Seoup Lee

Jin Su Kim

Jae Suk Sung

Woon Chun Kim

Young Hoon Kwak

Jong Man Kim

Chang Seob Hong

Ji Man Ryu

Jong Woo Han

In Kyung Park

Hyun Seop Shim

Woon Bong Joh

Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode. A method of fabricating the wafer level package having a cylindrical capacitor is also provided.

Wafer level package having cylindrical capacitor and method of fabricating the same

Disclosed herein is a semiconductor package, including: a first heat radiating plate; a second heat radiating plate formed below the first heat radiating plate; a heat radiating lead formed above the first heat radiating plate and having both ends contacted with the second heat radiating plate; an insulating layer formed above the heat radiating lead; at least one power device formed above the insulating layer; and at least one control device formed above the insulating layer.

Semiconductor package

Disclosed herein is a semiconductor chip, including: a first substrate having a concave formed on one surface thereof and an opening formed on a bottom surface of the concave; a second substrate contacting the other surface of the first substrate; and a semiconductor chip mounted in the concave.

Semiconductor package and method for manufacturing the same and semiconductor package module having the same

Disclosed herein are a method of attaching a die using a self-assembling monolayer and a package substrate including a die attached thereto using a self-assembling monolayer. A first self-assembling monolayer formed on a die and a second self-assembling monolayer formed on a substrate are provided with the same hydrophilic or hydrophobic functional group, so that the die is attached to the substrate using an attractive force acting between the first and second self-assembling monolayers. An accuracy of alignment between the die and the substrate can be improved by the simple solution.

Method of attaching die using self-assembling monolayer and package substrate including die attached thereto using self-assembling monolayer

Disclosed herein is an apparatus and method for inspecting defects in the circuit pattern of a substrate. The apparatus for inspecting defects in a circuit pattern of a substrate includes a pin probe configured to input a voltage while coming into contact with an inspection target circuit pattern of a substrate. A capacitor sensor is provided with a membrane electrode which is opposite a connection circuit pattern to be electrically connected to the inspection target circuit pattern in a non-contact manner, and is configured to detect both capacitance and capacitance variation, generated due to displacement of the membrane electrode attributable to electrostatic attractive force acting from the connection circuit pattern on the membrane electrode. A capacitance measurement unit is connected to the capacitor sensor and is configured to measure capacitance attributable to the displacement of the membrane electrode, which is input from the capacitor sensor.

Apparatus and method for inspecting defects in circuit pattern of substrate

There is provided a radio frequency identification (RFID) tag. The RFID tag includes a base formed of an insulating material, a circuit chip adhered to one surface of the base and including a pad for an electrical connection, and an antenna formed by jetting a conductive material onto the one surface of the base and electrically connected to the pad.

Growing community of inventors

Gyunggi-do, South Korea

Soon Gyu Yim