Nxp B.v.

Soon-Gil Jung

Siamak Delshadpour

Ahmad Yazdi

Xu Zhang

Xiaoqun Liu

Xueyang Geng

A wide band communications circuit buffer can include a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module, and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the emitter followers before an output of the wide band driver to keep an output level at the output of the wide band buffer close to a desired level. Resistors connected between emitters and a Vterminal can be used to further adjust the DC level. An LC tank filter can be provided between emitters of the voltage buffer components and the circuit's outputs to pass and boost high frequency signals provided to next stage components. The wide band buffer is, inter alia, appropriate for use in providing a DC level shift function as used in wired data communication systems circuitry.

Wide band buffer with DC level shift and bandwidth extension for wired data communication

A redriver powers up a high-speed channel within a time window sufficient to satisfy the requirements of a CIO mode of operation. The redriver includes a signal detector for a channel and control logic to activate the channel within a time window that satisfies operation in a CIO mode. The control logic may activate the channel by controlling a first bias current for a first circuit of the channel based on a signal detected by the signal detector. The first bias current may be greater than a second bias current for the first circuit during a mode different from the CIO mode. These features may form any linear or limiting redriver for a faster power-up time.

Fast response high-speed redriver channel power up in CIO mode

A signal detector includes an input to receive a differential signal, a generator to generate a first voltage based on the differential signal and a second voltage based on the first voltage and a predetermined voltage, and an output stage to output a detection signal based on the first voltage and the second voltage. The differential signal includes a first signal and a second signal. The detection signal has a first value when a difference between the first and second signals is in a first range and a second value when the difference between the first and second signals is in a second range. The detection signal may indicate the presence or absence of low frequency periodic signaling for the differential signal. Such a detector may demonstrate fast response and operate at low-current.

Signal detector

Embodiments of linear equalizers are disclosed. In an embodiment, a linear equalizer includes sets of transistors, a resistor, and first and second impedance elements. The sets of transistors are connected between at least one input terminal of the linear equalizer and at least one output terminal of the linear equalizer. The resistor is connected to a supply voltage, to the at least one output terminal, and to the sets of transistors. The first and second impedance elements are connected between emitter terminals or source terminals of the sets of transistors and at least one fixed voltage. A peaking gain of the linear equalizer is programmable by adjusting a direct current (DC) component of at least one input signal that is received at the at least one input terminal and that is applied to the sets of transistors.

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Cupertino, CA, United States of America

Soon-Gil Jung