Nxp USA, Inc.

Nxp B.v.

Micrel, Incorporated

Soon G Lim

Ranga Seshu Paladugu

Carmelo Morello

Hanqing Xing

Ronak Prakashchandra Trivedi

Menping Chang

The disclosure relates to improvements in bidirectional power switch circuits. Example embodiments include a bidirectional power switch, BPS, circuit () comprising: first and second terminals (); first and second MOSFETs () connected in series between the first and second terminals () and comprising respective first and second source to body diodes (Dsb, Dsb, Dsb); first and second power supply rails (VDD, VEE); first, second, third, fourth and fifth switchable current sources (IDD-, SD-, IEE-, SE-); first and second resistors (Rbs, Rgs); and a BPS switching controller () configured to control operation of the BPS circuit () between a BPS ON state in which the first and second terminals () are connected and a BPS OFF state in which the first and second terminals () are disconnected.

Bidirectional power switch circuit

The present disclosure relates to a high voltage bidirectional power switch circuit that includes a high voltage block coupled to a first terminal; and a resistance network including modules connected in parallel with each other between the high voltage block and a second terminal. Each module includes a precision resistor connected in series with a conduction channel of a resistance switching transistor; a first biasing resistor connected between a first conduction channel terminal and a control terminal of the resistance switching transistor; a second biasing resistor connected between a second conduction channel terminal and the control terminal; a body bias control circuit configured to control a bias of body diodes of the resistance switching transistor; a switchable sourcing current source; and a switchable sinking current source. Switches of the switchable sourcing current source and the switchable sinking current source receive switching signals to control the resistance switching transistor.

High voltage switch

A method for a fast settling ripple reduction loop for high speed precision chopper amplifiers includes amplifying an input signal with a signal path to generate a first output, the signal path comprising chopping the input signal to generate a first chopper output, amplifying the first chopper output with an amplifier to generate an amplifier output and chopping the amplified output to generate a second chopper output. An output ripple of the first output is reduced with a Ripple Reduction Loop comprising chopping the second chopper output to generate a third chopper output, filtering the third chopper output with a filter to generate a Direct Current (DC) offset correction, and combining the DC offset correction with the amplifier output, wherein the third chopper output is driven to the output voltage of the filter and the RRL is disconnected from the low frequency signal path in response to a non-linear event.

Fast settling ripple reduction loop for high speed precision chopper amplifiers

An integrated circuit includes a multiplexer circuit configured to provide an output signal on a conductive line, a programmable gain amplifier having a non-inverting input connected to the conductive line to receive the output signal from the multiplexer, a slew rate adjust circuit connected at a first node on the conductive line between the multiplexer circuit and the programmable gain amplifier, a first switch including a first terminal connected to the first node and a second terminal connected to the input of the programmable gain amplifier, and a low pass filter connected between the first and second terminals of the first switch.

Integrated circuit with an input multiplexer system

A line driver includes current sources and resistors that form a bridge circuit in which a bridge resistor is connected between an internal node and ground, and a series resistor connected between the internal node and the driver's output node. The internal node is connected to receive a unit current from a first stage transistor, and the output node is connected to receive an amplified current from a second stage transistor that is N times the unit current. The bridge resistor is formed with a resistance value set such that the voltages at the internal node and the output node are equal, i.e., such that no current flows through the series resistor. The resistance value of the series resistor is thus adjustable to optimize output impedance in a manner independent of the driver's gain. An echo cancellation circuit is utilized to eliminate noise from two associated line drivers.

Growing community of inventors

San Jose, CA, United States of America

Soon G Lim