Samsung Electronics Co., Ltd.

Soon-Deok Jang

Seung-Jin Seo

Young-Man Ahn

You-Keun Han

Seok-Il Kim

Jung-Kuk Lee

Jong-Cheol Seo

Seung-Hee Mun

A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal.

Memory module including memory buffer and memory system having the same

A memory module and related method are disclosed. The memory module comprises a clock generator configured to generate first and second internal clock signals in relation to an external clock signal, and a register configured to receive the first and second internal clock signals. The register stores an external control/address signal in response to the first internal clock signal and transmits an internal control/address signal derived from the external control/address in response to the second internal control/address signal.

Memory system with registered memory module and control method

Growing community of inventors

Yongin-si, South Korea

Soon-Deok Jang