Skyechip Sdn Bhd

Soon Chieh Lim

Chee Hak Teh

Yu Ying Ong

Tat Hin Tan

Hoong Chin Ng

Muhamad Aidil Bin Jazmi

Weng Li Leow

Yeong Tat Liew

Tze Jian Chow

Selvakumar Sivarajah

Ching Liang Ooi

Ging Yeon Mark Wong

Chuen Heong Khuan

Zhen Peng Chok

How Hwan Wong

Cheau Nih Tan

The present invention relates to a system (or) for aligning a programmable clock or strobe. The system (or) comprises a first programmable delay unit () for receiving the programmable clock or strobe, characterized by a second programmable delay unit () connected in parallel to the first programmable delay unit () for receiving the programmable clock or strobe, a switch () for switching one of the two programmable delay units (or) to service the programmable clock or strobe so as to allow the other programmable delay unit (or) to adjust the other programmable clock or strobe, and a control logic component () for handling the switching of the switch (), in which the switch () swaps in the adjusted programmable clock or strobe to service a downstream clocktree or strobe path after the programmable clock or strobe is adjusted. The present invention also relates to a method for aligning a programmable clock or strobe.

System and a method for aligning a programmable clock or strobe

The present invention relates to a system for network-on-chip power management. The system comprising a primary network-on-chip comprises multiple components, each component having a power controller, characterized by a secondary network-on-chip comprises a secondary network-on-chip master node and a plurality of secondary network-on-chip nodes connected thereto, the plurality of secondary network-on-chip nodes associated to the components of the primary network-on-chip for power managing individual and link components of the primary network-on-chip, and a power management unit connected to the secondary network-on-chip master node, configured to polling status registers of the components of the primary network-on-chip for accessing power states of each component, accessing routing information of the components of the primary network-on-chip and sending request to the secondary network-on-chip nodes for powering on or off the associated components of the primary network-chip through the power controller. A method for network-on-chip power management is also disclosed herein.

System and a method for network-on-chip power management

A memory controller for improving data integrity and providing data security. The memory controller including a transmit data path to transmit write data to a memory device, the transmit data path comprising a scrambling component, wherein the scrambling component includes a scrambling logic and an exclusive OR logic, wherein the write data is divided into a first portion and a second portion, wherein input of the scrambling logic comprises the first portion of the write data and an address associated with the write data to generate a pseudo-random output, and wherein input of the exclusive OR logic comprises the second portion of the write data, the pseudo-random output and a fixed seed corresponding to the first portion of the write data to generate a scrambled data.

Memory controller for improving data integrity and providing data security and a method of operating thereof

A method comprises the steps of receiving input from a user via user interface and selecting a plurality of flits from a plurality of ingress into a plurality of virtual channels followed by selecting the flits from the virtual channels into a plurality of egress based on the input from the user. The selection of the flits into the virtual channels and the egress characterized by the steps of computing default and elevated bandwidths of the virtual channels, computing default and elevated weights of the virtual channels based on the default and elevated bandwidths and generating a weightage lookup table using the default and elevated weights to perform arbitration weightage lookup for the flits with default and elevated priority levels for selecting the flits into the virtual channels and the egress, wherein the flits from the different ingress comprise different default and elevated weight.

Method and a system for network-on-chip arbitration

The present invention relates to a system and method for transferring configuration, management, debug information and asynchronous events between network-on-chip (NOC) and external interface, wherein said system, referred to as secondary network (), comprises of a plurality of configuration bus (CBUS) network elements such as a master network element () and a plurality of basic network elements (); whereby said secondary network () is capable to convey events such as request, acknowledge assertions or de-assertions, saving the need for numerous wires connecting between main NOC elements such as nodes or routers.

System and method for transferring configuration, management, debug information and asynchronous events between network-on-chip (NOC) and external interface

The present invention relates to a method and apparatus of calibrating memory interface, wherein said method and apparatus is able to periodically re-adjust the placement of the receive enable signal in order to have said receive enable signal to be in an optimum position in relation to the DQS signal from an external memory device to achieve maximum timing margin regardless of voltage or temperature drift and/or process aging to the integrated circuit.

Method and apparatus of receive enable margining in memory interface

An apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops (PLLs). The apparatus coupled within each PLL comprises: a local counter configured to provide a count when receiving a reference clock signal; a comparator configured to compare the count from the local counter with a predetermined or preconfigured value; wherein a multiplexor connected to the local counter and counters of adjacent PLLs, configured to select the count from the local counter or a count from the counters of the adjacent PLLs; wherein the selected count from the multiplexor is incremented and directed to the local counter; wherein an output clock divider enable is asserted to the PLL to start an output clock divider to generate the output clock signal when the count from the local counter reaches the predetermined or preconfigured value.

Apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops

A memory sequencer system for external memory protocols including a control center and a microcontroller; a control center network-on-chip having nodes connected point-to-point to synchronize and co-ordinate communication; whereby a command and address sequencer to generate command, control and address commands for specific memory protocols; and at least one data sequencer to generate pseudo-random or deterministic data patterns for each byte lane of a memory interface; wherein said command and address sequencer and said data sequencer are chained to form complex address and data sequences for memory interface training, calibrating and debugging; wherein said control center network-on-chip interconnecting the control center with said command and address sequencer and data sequencer to provide firmware controllability.

Memory sequencer system and a method of memory sequencing using thereof

A generic physical layer providing a unified architecture for interfacing with an external memory device. The physical layer comprises a transmit data path for transmitting a parallel data to the external memory device and a receive data path for receiving a serial data from the external memory device. The generic physical layer is characterized by a receive enable logic for masking strobe of the serial data, wherein the transmit data path and the receive data path each comprising a FIFO circuit, a data rotator and an adjustable-delay logic for delay tuning and a per-bit-deskew for multi-lane support.

Generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device

An apparatus and a method for handling non-continuous data transfer for a decision feedback equalizer in a memory subsystem. The apparatus includes a plurality of end-of-transfer detection flip-flops configured to sample a read data enable signal; a flag flip-flop; a first logic circuit configured to generate a load enable signal in response to the end-of-transfer detection flip-flops and the flag flip-flop; a second logic circuit configured to generate a load data in response to the end-of-transfer detection flip-flops, the flag flip-flop and the read data enable signal; a plurality of first-in-first-out buffers configured to receive the load enable signal and the load data, and unload the load data as an end-of-transfer indicator in line with data strobe; and a plurality of bypass flip-flops configured to generate a bypass signal in response to the end-of-transfer indicator.

Apparatus and a method for handling non-continuous data transfer for a decision feedback equalizer in a memory subsystem

A I/O transmitter circuitry for supporting multi-modes serialization comprising a serializer, wherein said serializer comprising a multiple FIFO buffers, a multiple flip-flops including a first latch, a second latch, a third flop and a fourth flop, to hold data ready and stage the data for subsequent muxing, a 0-degree shifted clock and a 90-degree shifted clock and a multiplexer, wherein a read pointer reads one bit of data from each of the FIFO buffers, wherein the data is sampled into the respective flip-flops according to frequency of the 0-degree shifted clock and 90-degree shifted clock, wherein the data is outputted by the 0-degree shifted clock and 90-degree shifted clock via the multiplexer.

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Pulau Pinang, Malaysia

Soon Chieh Lim