Intel Corporation

Easic Corporation

Soon Chieh Lim

Jonathan C Park

Loo Shing Tan

Yit Ping Kok

Herman Henry Schmit

Jose M Rodriguez

Yin Hao Liew

Ying Wei Liew

Choon Keat Khor

Kok Lim Patrick Lee

Shu Ern Perng Mark

Wai Leng Chek

Yeong Seng Hoo

King Heng Lock

A clock signal may be aligned with a data signal by delaying the signals relative to each other until an edge of one signal aligns with an edge of the other signal, and then causing an inversion of the clock signal. A further variation may limit the relative delay period to one-half clock cycle and may use a double inversion of the clock signal.

Dynamic phase alignment

Techniques that may be utilized in a multiprocessor system to reduce power consumption are described. In one embodiment, one or more internal components of a processor core are clocked at least partially by a frequency controlled clock signal.

Reducing power consumption in multiprocessor systems

A configurable logic array may include a multiplicity of logic components, which may contain customizable look-up tables, and layers of fixed metal segments all of which may be customizable using a single custom via layer. The integrated circuit containing the configurable logic array may also include a multiplicity of customizable register files, customizable RAM blocks; a ROM block with customizable contents; or test logic with customizable test options and configurations to separately test logic and the PLLs.

Single via structured IC device

A method for verifying library components and designs on a via customizable ASIC, which may include the process of adding capacitors to model possible via sites of a model of an un-customized portion of or a whole ASIC, and replacing the capacitors with resistors to model where custom vias have been placed on the ASIC to implement a desired component or design. Views of this model may then be generated to verify the functionality of the component or design, and component models for timing, function and via customization may then be generated for the component library.

Programmable via modeling

A method and apparatus to support communication between components in different clock domains having a rational clock frequency ratio of N/D. In one embodiment, a combination of integer phase generators are employed to produce phase control signals during an overall cycle having N phases, wherein the overall cycle is a combination of primary cycles having D phases and an adjustment cycle having R phases, wherein R is the remainder of N/D. For clock frequency ratios of less than 2:1, a combination of 2:1 and 1:1 phase generators are employed. Clocking signals are generated by phase generator logic to provide timing control between communicating components in the different clock domains. In one embodiment, the phase generator logic is implemented in a programmable phase generator.

Programmable phase generator for cross-clock communication where the clock frequency ratio is a rational number

In one embodiment, a method is provided in which an integrated circuit that includes an integrated input/output (I/O) controller is coupled to a storage system. The integrated circuit is coupled to a host processor system bus via a dedicated communication path. The storage system is capable of being coupled to and de-coupled from at least one removable storage device, and of receiving from the integrated circuit, when the storage system is coupled to the integrated circuit, data and/or an I/O request. The method of the embodiment also includes coupling or de-coupling the at least one removable storage device to or from, respectively, the storage system. The storage system remains capable of receiving from the integrated circuit the data and/or I/O request while the at least one removable storage device is being coupled to or de-coupled from the storage system.

Growing community of inventors

Penang, Malaysia

Soon Chieh Lim