International Business Machines Corporation

Globalfoundries Inc.

Elpis Technologies Inc.

Infineon Technologies Ag

Adeia Semiconductor Bonding Technologies Inc.

Other

Adeia Semiconductor Solutions LLC

Tessera LLC

Soon-Cheon Seo

Injo Ok

Balasubramanian Pranatharthiharan

Choonghyun Lee

Alexander Reznicek

Seyoung Kim

Kangguo Cheng

Charan V V S Surisetty

Youngseok Kim

Charan V Surisetty

Takashi Ando

Ali Khakifirooz

Tenko Yamashita

Sivananda K Kanakasabapathy

Chih-Chao Yang

Fee Li Lie

Hong He

Dexin Kong

Bruce Bennett Doris

Sanjay C Mehta

Hiroyuki Miyazoe

Linus Jang

Effendi Leobandung

Chanro Park

Oleg Gluschenkov

Ramachandra Divakaruni

Eric R Miller

Yun-Yu Wang

Gauri V Karve

Derrick Liu

Ruilong Xie

Theodorus E Standaert

Chun-chen Yeh

Shogo Mochizuki

Min Gyu Sung

John Ryan Sporre

Balasubramanian S Haran

Muthumanickam Sankarapandian

Stuart A Sieg

Stephen Edward Greco

Kwong Hon Wong

Raghavasimhan Sreenivasan

Timothy Mathew Philip

Brett H Engel

Lawrence Alfred Clevenger

Anthony K Stamper

Brent A Anderson

Yun Yu Wang

Hariklia Deligianni

Joel Pereira De Souza

Andrew Herbert Simon

Babar Ali Khan

John Anthony Fitzsimmons

Eduard Albert Cartier

Tze-Chiang Chen

Vincent James McGahay

Erdem Kaltalioglu

Indira P Seshadri

Carlos Juan Sambucetti

Panayotis Constantinou Andricacos

James John Kelly

Terence Lawrence Kane

Pietro Montanini

Erick G Walton

Mark Hoinkis

Ryan O Jung

Tuan Anh Vo

Kisup Chung

Veeraraghavan S Basker

Haining S Yang

Vijay Narayanan

Shom Ponoth

Hemanth Jagannathan

Julien Frougier

Lars W Liebmann

Wenyu Xu

Timothy Joseph Dalton

Hsueh-Chung Chen

Yann Mignot

Ravikumar Ramachandran

Chi-Chun Liu

Xuefeng Liu

Stephen Mark Rossnagel

Emre Alptekin

Chun-Chen Yeh

Naftali Eliahu Lustig

Paul Charles Jamison

Nicole A Saulnier

Shyng-Tsong Chen

Mahadevaiyer Krishnan

Kaushik Arun Kumar

Raghuveer Reddy Patlolla

Chao-Kun Hu

Douglas C La Tulipe, Jr

Darryl D Restaino

Christopher Carr Parks

John A Miller

Balasubramanian S Pranatharthi Haran

Derren Neylon Dunn

Mickey H Yu

A resistive memory includes: a bottom electrode; a first contact on the bottom electrode; a switching material pad on the first contact, wherein the switching material pad includes an oxide and a plurality of current conducting filaments in the oxide; a top electrode on the switching material pad; a plurality of sacrificial vias contacting the bottom electrode; a second contact that is connected to the bottom electrode; and a third contact that is connected to the top electrode.

Redundant bottom pad and sacrificial via contact for process induced RRAM forming

A memory device including a trench to a first electrically conductive structure; a first electrode of a conformal electrically conductive material contained within the trench in electrical communication with the first electrically conductive structure and is present on sidewalls of the trench; a switching layer is present in the trench on the first electrode and extends outside the trench; and a second electrode present on the switching layer overfilling the trench. The memory device also includes a contact positioned on a portion of the second electrode that is overfilling the trench to provide that the contact is horizontally offset from the first electrode that is present in the trench.

Top contact on resistive random access memory

Embodiments of present invention provide a method of forming a resistive random-access memory (RRAM). The method includes forming a dielectric layer on top of a supporting structure, wherein the dielectric layer has a bottom electrode embedded therein; forming an oxide layer on top of the bottom electrode; treating the oxide layer in a plasma environment; forming a top electrode on top of the oxide layer; forming a first interlevel-dielectric (ILD) layer on top of the top electrode; forming a via contact and a first metal layer in the first ILD layer, wherein the first metal layer is in contact with the top electrode through the via contact; forming a capping layer on top of the first metal layer through a plasma-enhanced deposition process; and causing formation of one or more filaments in the oxide layer during the plasma-enhanced deposition process. A structure of the RRAM is also provided.

Process-induced forming of oxide RRAM

A memory structure comprises a ReRAM module embedded in a substrate. An insulative layer is formed on the substrate. A first electrode is located on the insulative layer. The first electrode is proximately connected to a first end of the ReRAM module and comprises a first surface area. A second electrode is located on the insulative layer. The second electrode is proximately connected to a second end of the ReRAM module. The second electrode comprises a second surface area, a plasma-interacting component, and a resistive component. The resistive component is located between the plasma-interacting component and the ReRAM module. A ratio of the first surface area to the second surface area creates a voltage between the first electrode and second electrode when the first surface area and second surfaces area are exposed to an application of plasma. The voltage forms a conductive filament in the ReRAM module.

Antenna assisted ReRAM formation

A semiconductor device includes a PCM stack that includes bottom electrode liner over a lower heater. The bottom electrode liner has a top-down view plus (+) geometry with a 'horizontal' portion being orthogonal to a ‘vertical’ portion. An airgap is formed within the PCM stack in an area located adjacent and between the ‘horizontal’ portion and the ‘vertical’ portion. The airgap has a substantially smaller dielectric constant than the surrounding PCM stack material(s). Therefore, the airgap may effectively reduce the amount of current that leaks from the PCM stack when flowing from the bottom electrode liner to a top contact or top electrode. Further, the airgap may allow for expansion of the surrounding PCM stack material(s) that may result from the heating of the PCM stack.

Phase change memory programming current leakage reduction

A semiconductor structure comprises a first transistor, a second transistor vertically stacked over the first transistor, a source/drain region shared between the first transistor and the second transistor, and a resistive random-access memory device connected to the shared source/drain region.

Resistive random-access memory structures with stacked transistors

Arrays of PCM devices and techniques for fabrication thereof having an integrated resistor formed during heater patterning for uniform voltage drop amongst the PCM devices are provided. In one aspect, a PCM device includes: at least one PCM cell including a phase change material disposed on a heater; and at least one resistor in series with the at least one PCM cell, wherein the at least one resistor includes a same combination of materials as the heater. A memory array and a method of forming a PCM device are also provided.

Uniform voltage drop in arrays of memory devices

A PCM cell includes a first electrode, a heater/PCM portion electrically connected to first electrode, the heater/PCM portion comprising a PCM material, a second electrode electrically connected to the PCM material, and an electrical insulator stack surrounding the projection liner. The stack includes a plurality of first layers comprised of a first material and having a plurality of first inner sides facing towards the projection liner, and a plurality of second layers alternating with the plurality of first layers, the plurality of second layers comprised of a second material that is different from the first material, and the second plurality of layers having a plurality of second inner sides facing towards the projection liner. The plurality of second inner sides that are offset from the plurality of first inner sides forming a plurality of gaps.

Phase change memory gaps

A semiconductor device comprises a plurality of resistive memory element structures, at least a subset of the plurality of resistive memory element structures being associated with random analog resistive states. The random analog resistive states of the subset of the plurality of resistive memory element structures provide a unique identification of the semiconductor device.

Semiconductor device identification using preformed resistive memory

A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack

Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a charge-particle-treated memory stack over the metal interconnect electrode. The charge-particle-treated memory stack includes a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode. The dielectric layer includes a portion of a blanket dielectric layer. The bottom electrode includes a portion of a blanket bottom electrode layer. The charge-particle-treated memory stack further includes a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

Oxide-based resistive memory having a plasma-exposed bottom electrode

A semiconductor structure, and a method of making the same includes a fin extending upward from a substrate, an epitaxially grown bottom source/drain region in direct contact with the substrate and a bottom portion of the fin. A bottom surface and sidewalls of a metal silicide layer are in direct contact with the epitaxially grown bottom source/drain region. A bottom spacer is located above and in direct contact with the metal silicide layer and a portion of the epitaxially grown bottom source/drain region not covered by the metal silicide layer, the bottom spacer surrounding the fin.

Vertical field effect transistor with low-resistance bottom source-drain contact

A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a bottom electrode and a top electrode separated by a dielectric film. A portion of the dielectric film directly above the bottom electrode may be doped and crystalline. The semiconductor structure may include a stud below and in electrical contact with the bottom electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Back end of line embedded RRAM structure with grain growth enhancement

A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Back end of line embedded RRAM structure with low forming voltage

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Structure and process to tuck fin tips self-aligned to gates

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Soon-Cheon Seo