Samsung Electronics Co., Ltd.

Seoul National University

Snur & Db Foundation

Korea Advanced Institute of Science and Technology

Soojung Ryu

Yeongon Cho

Sangheon Lee

Seokyoon Jung

Jeongjoon Yoo

Jeongae Park

Jeongwook Kim

Woong Seo

Dong Kwan Suh

John Wakefield Brothers

Dong-hoon Yoo

Sundeep Krishnadasan

Changmoo Kim

Il Han Park

Sangoak Woo

Seunghun Jin

Kiyoung Choi

Jong Myon Kim

Sunjung Lee

Seung Wook Lee

Minsu Ahn

Dong-Hoon Yoo

Seungin Park

Wonjong Lee

Dongwoo Lee

Kwontaek Kwon

Hyeongseok Yu

Kyoung June Min

Jintaek Kang

Haewoo Park

Hyongeuk Lee

Choon Ki Jang

Jaehyun Kim

Jun Jin Kong

Hee Seok Kim

John Dongjun Kim

Hong-Seok Kim

Jaedon Lee

Jongpil Son

Seok Hyun Kang

Donghoon Yoo

Yoonseo Choi

Suk Jin Kim

Keshavan Varadarajan

Seungcheol Baek

Minyoung Son

Minkyu Jeong

Yeon Gon Cho

Minseok Lee

Krishnadasan Sundeep

Mookyoung Chung

A memory controller includes a dirty group detector configured to, in response to receiving a request for writing data to a memory, modify addresses of a cache group related to a physical address of the memory, increase counters corresponding to the modified addresses of the cache group, and detect whether the cache group is in a dirty state based on the counters; and a dirty list manager configured to manage the cache group in the dirty state and a dirty list including dirty bits according to a result of the detecting; wherein the dirty bits indicate whether a cache set included in the cache group is in the dirty state.

Method and device for controlling memory

An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned on an accelerator, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.

Operation method of an accelerator and system including the same

An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned by a host controller, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.

A method of rendering at least one of paths forming an object includes setting an initial value to each of tiles included in a frame based on a position and a proceeding direction of the at least one of paths, calculating a winding number of each of the tiles through which the at least one of paths passes, among the tiles included in the frame, based on the set initial value, and determining whether to perform shading based on the set initial value and the calculated winding number.

Method and apparatus for performing tile-based path rendering

In a method and device to align phases of a first clock signal and a second clock signal, include a phase detector, a delay generator, and a controller. The phase detector is configured to generate a preceding signal and a succeeding signal with respect to the first clock signal to detect a relationship between phases of the first clock signal and the second clock signal. The delay generator is configured to delay the first clock signal when the second clock signal falls behind the succeeding signal with respect to the first clock signal. The controller is configured to determine whether the phases of the first clock signal and the second clock signal are aligned with each other according to the relationship detected by the phase detector.

Method and device to align phases of clock signals

A rendering method includes receiving an input including pixel pattern information of a device configured to display a rendered image, generating a pixel pattern of the rendered image using the received input indicating pixel pattern information, and outputting a pixel value of the rendered image into a frame buffer using the generated pixel pattern.

Rendering method, rendering apparatus, and electronic apparatus

A rendering method includes generating mipmap images of some levels with respect to texture and storing the generated mipmap images in a storage, receiving a request for the texture, calculating a level of a mipmap requested for the texture, determining whether the stored mipmap images include the mipmap image of the calculated level, and performing rendering by using at least one of the stored mipmap images, based on a result of the determining.

Method and apparatus for rendering

A texture processor includes: a texture cache configured to store textures; a controller configured to determine a texture address corresponding to a requested texture among the stored textures and read a texture corresponding to the texture address from the texture cache; a format converter configured to convert a format of the read texture into another format, based on a degree of texture precision required by a graphics processing unit (GPU); and a texture filter configured to perform texture filtering using the read texture having its format converted into the another format.

Texture processing apparatus and method

A computing system includes a memory device comprising a memory array and an internal processor configured to perform a first sub pipeline of a graphics pipeline for tile-based rendering by using graphics data stored in the memory array, for offload processing of the first sub pipeline from a host processor; and the host processor configured to perform a second sub pipeline of the graphics pipeline by using a result of the first sub pipeline stored in the memory array.

Computing system and method of performing tile-based rendering of graphics pipeline

A method of performing path rendering, includes acquiring information of vertexes in an object to be rendered in a frame, and calculating a winding number of a pixel in the frame, based on a relationship between a position of the pixel and a proceeding direction of a path connecting the vertexes. The method further includes determining whether to assign a color to the pixel, based on the winding number.

Method and apparatus for performing path rendering

A method of executing a graphics pipeline includes calculating, while executing the graphics pipeline on a current frame, a resource for processing properties of an object included in a following frame, determining, based on a result of the calculating, whether to perform a pre-process for the object included in the following frame, performing the pre-processing, when the pre-process is determined to be performed, comprising transforming the properties of the object that are to be processed in a graphics pipeline for the following frame, and executing, when the pre-process is to be performed, the graphics pipeline for the following frame by using the transformed properties of the object.

Method and apparatus for executing graphics pipeline

A texture processing method of processing a compressed texel block in which texels constituting a texture are compressed into a predetermined block unit includes obtaining, based on the compressed texel block, a representative value of texels constituting a texel block, a weight for each of the texels constituting the texel block, and an index of the representative value and the weight corresponding to each of the texels constituting the texel block; storing the representative value, the weight, and the index in a texture cache; reading the representative value and the weight from the texture cache according to an index corresponding to a requested texel; generating texels based on the read representative value and the read weight; and performing texture filtering using the generated texels.

Texture processing method and unit

Growing community of inventors

Hwaseong-si, South Korea

Soojung Ryu