Samsung Electronics Co., Ltd.

International Business Machines Corporation

Globalfoundries Inc.

Soojae Park

Michael A Gaynes

Edward John Yarmchuk

Maurice McGlashan-Powell

Kyujin Lee

Jae-Woong Nah

Sri Muthuthamby Sri-Jayantha

Claudius Feger

Paul Francis Fortier

Kang-Wook Lee

Keunwoo Kim

Jongwoo Park

Jichul Kim

Geunwoo Kim

Yunhyeok Im

Kyol Park

Eon Soo Jang

Jin-Kwon Bae

Seungbae Lee

Junghyun Roh

Sangsu Ha

Younhee Kang

Pascal P Blais

HyunSuk Chun

Keunho Jang

Younjo Mun

Hyunsuk Chun

Robert L Toutant

Alain A Warren

A capacitor wire includes a core electrode line provided in the form of a wire, an outer electrode line covering at least a portion of the core electrode line, and a dielectric line interposed between the core electrode line and the outer electrode line. The outer electrode line comprises material having a melting point lower than material of the core electrode line.

Capacitor wire and electronic device including the same

A wiring board includes an insulating layer having a first surface and a second surface, which are opposite to each other, upper wiring patterns on the first surface of the insulating layer, lower wiring patterns on the second surface of the insulating layer, intermediate wiring patterns, which are disposed in the insulating layer and are electrically connected to the upper wiring patterns and the lower wiring patterns, and a capacitor wire connected to corresponding wiring patterns of the upper wiring patterns, the lower wiring patterns, and the intermediate wiring patterns. The capacitor wire includes a core electrode line having a wire shape, an outer electrode line covering at least a portion of the core electrode line, and a dielectric line interposed between the core electrode line and the outer electrode line.

Capacitor-wire-embedded wiring board

A chip capacitor includes a substrate, a plurality of capacitor wires on the substrate, and a mold layer disposed on the substrate to cover the capacitor wires. Each of the capacitor wires includes a core electrode line having a wire shape, an outer electrode line covering at least a portion of the core electrode line, and a dielectric line interposed between the core electrode line and the outer electrode line.

Chip capacitor including capacitor wires

A semiconductor package includes a semiconductor substrate, a conductive pad on the semiconductor substrate, a redistribution line conductor, a coating insulator, and an aluminum oxide layer. The redistribution line conductor is electrically connected to the conductive pad. The coating insulator covers the redistribution line conductor and partially exposes the redistribution line conductor. The aluminum oxide layer is provided below the coating insulator and extends along a top surface of the redistribution line conductor, and the aluminum oxide layer is in contact with the redistribution line conductor.

Semiconductor package and method of fabricating the same

The substrate includes one or more bottom circuit (BC) layers disposed one upon another and one or more front circuit (FC) layers disposed one upon another. The FC layers are disposed on the BC layers. In some embodiments, there are one or more core layers disposed between the FC and BC layers. One or more soft zones are located within and penetrate through one or more of the FC layers. Each soft zone has a soft zone volume which is made of one or more component volumes located in each of one or more of the FC layers. Each soft zone component volume has a soft zone cross sectional area. The soft zone cross sectional areas are located inside a chip boundary projection. The chip boundary projection is a vertical projection of one or more sides of a semiconductor chip through the FC layers. The soft zone volume contains a soft zone material with a Young's modulus that is less than 100 GigaPascals (GPa). Alternative embodiments are presented with outside soft zones outside the chip boundary projection.

Stress mitigation in organic laminates

A printed circuit board comprises an epoxy-containing member, a first copper pattern disposed adjacent to the epoxy-containing member, and a first adhesion promoter layer interposed between the epoxy-containing member and the first copper pattern.

Printed circuit board and semiconductor package including the same

A package frame includes a plurality of unit regions disposed on one surface of the package frame, a peripheral region surrounding the unit regions on the one surface, and a wrinkled structure disposed on the one surface in the peripheral region. A first surface of the wrinkled structure extends from the one surface and is disposed at a different level than the one surface. Each of the unit regions includes a plurality of conductive pads.

Package frame and method of manufacturing semiconductor package using the same

A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern disposed in the insulating layer and adjacent to the top surface of the insulating layer, at least one second copper pattern disposed on the bottom surface of the insulating layer, and at least one embedded aluminum pad disposed on the at least one first copper pattern, the at least one embedded aluminum pad disposed in the insulating layer such that a top surface of the at least one embedded aluminum pad is exposed by the insulating layer may be provided.

Package substrate, method for fabricating the same, and package device including the package substrate

Provided is a semiconductor package including a wiring substrate having top and bottom surfaces. A first semiconductor chip is disposed on the wiring substrate in a flip-chip manner. The first semiconductor chip has a first surface facing the top surface of the wiring substrate and a second surface opposite to the first surface. First connection members are disposed between the wiring substrate and the first semiconductor chip. The first connection members include first and second contact members each including one or more magnetic materials. The first contact members include portions disposed in the second contact members. The one or more magnetic material of the first contact members have an opposite polar orientation to that of the second contact members.

Semiconductor package having magnetic connection member

A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.

Method of joining a chip on a substrate

A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on the first semiconductor chip to expose at least a portion of the first semiconductor chip, and a stress-relieving structure provided at an edge of the first semiconductor chip and configured to relieve stress applied between the first semiconductor chip and the second semiconductor chip.

Semiconductor package

According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each other, a lower heat exhaust part between the lower package and the upper packages, an intermediate heat exhaust part between the upper packages and connected to the lower heat exhaust part, and an upper heat exhaust part on the upper packages and connected to the intermediate heat exhaust part.

Semiconductor packages including heat exhaust part

A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip.

Curvilinear heat spreader/lid with improved heat dissipation

Electrical finite element analysis is carried out on a circuit design, which includes devices, to determine an acceptable power-performance envelope and to obtain data for circuit temperature mapping. A circuit temperature map is developed for the circuit design, based on the data for circuit temperature mapping. Thermo-mechanical finite element analysis is carried out on a package design for the circuit design, based on the circuit temperature map, to determine a package reliability limit based on thermal stress considerations. It is determined whether the package design and the circuit design jointly satisfy: (i) power-performance conditions specified in the acceptable power-performance envelope; and (ii) the package reliability limit based on the thermal stress considerations.

Growing community of inventors

Asan-si, South Korea

Soojae Park