Samsung Electronics Co., Ltd.

Sooho Shin

Junghoon Han

Yeonjin Lee

Minjung Choi

Yoosang Hwang

Kiseok Lee

Jun Ho Lee

Keunnam Kim

Chan-Sic Yoon

Jemin Park

Myeong-Dong Lee

Hyeon-Woo Jang

Juik Lee

Kwangmin Kim

Hoin Lee

Ilyoung Moon

Bumseok Seo

Minsu Choi

Sunghee Han

Daeik Kim

Dong-sik Park

Yoonjae Kim

Hyo-sun Min

Cheolho Baek

A semiconductor device may include a substrate including a cell array region, a data storage structure provided on the cell array region of the substrate, the data storage structure including a bottom electrode, a top electrode on the bottom electrode, and a dielectric layer interposed between the bottom electrode and the top electrode, a blocking layer provided on a top surface of the top electrode, a lower interlayer insulating layer provided on the blocking layer, and a lower contact penetrating the lower interlayer insulating layer and electrically connected to the top electrode. At least a portion of a side surface of the lower contact may contact the blocking layer.

Semiconductor device

Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

Method of fabricating semiconductor memory device having protruding contact portion

A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

Semiconductor devices including a thick metal layer and a bump

A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 &#x3bc;m or more, and an upper surface of the protective insulating layer is planar.

Semiconductor memory devices having protruding contact portions

A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

Semiconductor devices with alignment keys

A method of fabricating a semiconductor device includes sequentially forming a first insulation pattern and an etch stop pattern on a peripheral circuit area of a substrate, forming a first mask pattern on a cell array area of the substrate, the first mask pattern including a pair of first portions extending in parallel and a second portion covering a portion of a sidewall of the etch stop pattern and a portion of a sidewall of the first insulation pattern, forming a second insulation layer covering the etch stop pattern and the first mask pattern, partially etching the etch stop pattern and the second insulation layer to expose the second portion of the first mask pattern, and removing the second portion of the first mask pattern to divide the pair of first portions of the first mask pattern.

Methods of fabricating semiconductor devices

A semiconductor memory device includes an active region protruding from a substrate. The active region includes first and second doped regions therein and a trench therein separating the first and second doped regions. A buried gate structure extends in a first direction along the trench between first and second opposing sidewalls thereof. A conductive interconnection plug is provided on the first doped region adjacent the first sidewall of the trench, and a conductive landing pad is provided on the second doped region adjacent the second sidewall of the trench. The landing pad has a width greater than that of the second doped region of the active region along the first direction. A conductive storage node contact plug is provided on the landing pad opposite the second doped region. The storage node contact plug has a narrower width than the landing pad along the first direction.

Semiconductor memory device including narrower storage node contact plugs

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Hwaseong-si, South Korea

Sooho Shin