Skhynix Inc.

Lg Electronics Inc.

Soo Young Jang

Geun Il Lee

Jin Youp Cha

Seung Hun Lee

Hyun Woo Lee

Sang Sic Yoon

Dae Han Kwon

Kyu Dong Hwang

Kyu Bong Kong

Yong Suk Joo

Kyung Ho Chu

A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.

Clock distribution circuit and semiconductor device including the clock distribution circuit

A system may include an external apparatus and a semiconductor apparatus. The semiconductor apparatus may be configured to communicate with the external apparatus by receiving a frequency-varying first clock signal provided from the external apparatus.

Semiconductor apparatus related to receiving clock signals having variable frequencies, and system including the semiconductor apparatus

A semiconductor apparatus includes a test entry control block configured to generate a plurality of trigger signals and a reset signal according to a test setting command and addresses; and a test entry signal generation block configured to enable a test entry signal when the plurality of trigger signals are sequentially enabled.

Semiconductor apparatus

A semiconductor apparatus includes: a pad unit comprising a plurality of data input/output (I/O) pads and a plurality of error detection code pads; an error detection code (EDC) read path configured to generate a plurality of EDCs by performing an error detection operation on a plurality of data, and output the plurality of EDCs through the plurality of error detection code pads; a comparison circuit configured to generate a comparison result signal by comparing the plurality of EDCs; and a data read path configured to output the comparison result signal through any one of the plurality of data I/O pads.

Semiconductor apparatus and test system including the semiconductor apparatus

A semiconductor apparatus includes a transmission device and a receiving device. The transmission device generates an output signal from a transmission signal in synchronization with a clock signal. The receiving device generates a reception signal from the output signal in synchronization with the clock signal and a delayed clock signal generated by delaying the clock signal by a preset time, based on an operating speed of the semiconductor apparatus.

Semiconductor apparatus for transmitting and receiving a signal in synchronization with a clock signal

A system may include a first semiconductor apparatus and a second semiconductor apparatus. Each of the first and second semiconductor apparatuses may receive reference data and a first clock signal. The first semiconductor apparatus may generate a first internal clock signal from the first clock signal, and may output the reference data as transmission data based on the first internal clock signal. The second semiconductor apparatus may generate a second internal clock signal from the first clock signal, and may receive the transmission data based on the second internal clock signal. The second semiconductor apparatus may generate an error detection signal based on the received data and the reference data.

Semiconductor apparatus and system relating to performing a high speed test in a low speed operation environment

A semiconductor memory apparatus may include a row address control block configured to output an address as a row address or output a counted signal as the row address in response to a refresh signal and the address, and generate an auto-precharge signal and a pre-bank active signal in response to the refresh signal and a bank active signal. The semiconductor memory apparatus may include a bank control block configured to generate the bank active signal in response to an active signal, a precharge signal, a bank address signal, the auto-precharge signal and the pre-bank active signal.

Semiconductor memory apparatus

A method for backward reproduction in a video tape recorder, includes the steps of detecting a position on a magnetic video tape where a video head contacts with the tape at the time when a backward reproduction instruction is inputted by the user, moving the tape in the reverse direction from the detected position, stopping the reverse movement of the tape immediately after a set amount of the tape, reproducing the video signal recorded on the tape while moving the tape in the forward direction, storing the reproduced video signal in the field memory after digitization, and generating a video signal by reading out stored video data from the field memory in the reverse sequence in which they have been stored as soon as the field memory becomes full. The present method allows review of high-quality images in backward reproduction of the recorded video signals using a simple servo control.

Method for backward reproduction in a time-lapse video recorder

In the method and apparatus for controlling an intermittent recording state, an operating mode is received from a user. The operating mode indicates an operation period and a pause period, wherein operations are performed on a tape medium during the operation period and no operation is performed on the tape medium during the pause period. The pause period is compared with a predetermined period of time, and if the pause period exceeds the predetermined period of time, the tape medium is disengaged from the recording/reproducing head of the recording/reproducing apparatus during the pause period and/or the rotation of the recording/reproducing head is stopped during the pause period.

Method and apparatus for controlling intermittent recording site

The present invention relates to a method for determining when a tape or a head drum is controlled to resume recording after recording pause period in time-lapse video tape recorder, comprising the steps of confirming a recording time in a time-lapse recording mode set by a user; calculating the maximum storage time, or the time required to store video frames maximally in a field memory based on the recording time; calculating the time elapsed since the video frames begun to be stored in the field memory while keeping storing the video frames; confirming whether the elapsed time is equal to the maximum storage time minus a recording preparation period; either reloading the tape that has been unloaded or rotating the head drum that has been stopped so as to record the video frames in the field memory according to the confirmation result. Thus, the video frames which have been stored maximally in the field memory are retrieved and recorded on the tape successively without waiting time needed to be ready for recording such as the time for either loading the tape or rotating the head drum at a normal rotation speed.

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Seoul, South Korea

Soo Young Jang