Applied Materials, Inc.

Applied Komatsu Technology, Inc.

Applied Material, Inc.

Soo Young Choi

John M White

Beom Soo Park

Tae Kyung Won

Robin L Tiner

Gaku Furuta

Lai Zhao

Jrjyan Jerry Chen

Suhail Anwar

Shinichi Kurita

Dong-Kil Yim

Qunhua Wang

Yujia Zhai

Xiangxin Rui

Sanjay D Yadav

Yi Cui

Carl A Sorensen

Yong Kee Chae

Jung Bae Kim

Quanyuan Shang

Jianheng Li

Chien-Teh Kao

Shuran Sheng

Takako Takehara

Li Hou

Robert I Greene

Liwei Li

Dong Kil Yim

Chung-Hee Park

Young Jin Choi

Jiarui Wang

Ki Woon Kim

Kam S Law

Seon-Mee Cho

Jozef Kudela

James Hoffman

Rodney Shunleong Lim

Jriyan Jerry Chen

Hong Soon Kim

Han Byoul Kim

Young Dong Lee

Omori Kenji

Young-jin Choi

Yan Ye

Lisong Zhou

William Reid Harshbarger

Ernst Keller

Allen K Lau

Sam Hyungsam Kim

Young Eun Lee

Yong-Kee Chae

Michael Starr

Jin Man Ha

Sangeeta Dixit

Ya-Tang Yang

Jiri Kucera

Remegio Manacio

Bora Oh

Carl Sorenson

Young-Jin Choi

David Atchley

Dan Maydan

Eric Andrew Englhardt

Jianhua Zhou

Dieter Haas

Byung-Sung Kwak

David Tanner

Robert Z Bachrach

Makoto Inagawa

Robert M Robertson

Danny Cam Toan Lu

Jeffrey S Sullivan

Yacov Elgar

Asaf Schlezinger

Jose Manuel Dieguez-Campo

Ilyoung R Hong

Xuena Zhang

William Norman Sterling

Stephen P Murphy

James Craig Hunter

Charles Gay

Helinda Nominanda

Jeffrey A Kho

Penchala N Kankanala

Fang Mei

Su Ho Cho

Fei Peng

Nicholas G J De Vries

Parris Hawkins

Tzay-Fa (Jeff) Su

Michel Ranjit Frei

Changling Li

Teresa Trowbridge

Dongsuh Lee

Ganesh Babu Chandrasekaran

Jinhyun Cho

Choi (Gene) Ho

Wing Hoo (Hendrick) Lo

Srujal (Steve) Patel

Embodiments of the present disclosure include methods and apparatus for depositing a plurality of layers on a large area substrate. In one embodiment, a processing chamber for plasma deposition is provided. The processing chamber includes a showerhead and a substrate support assembly. The showerhead is coupled to an RF power source and a ground and includes a plurality of perforated gas diffusion members. A plurality of plasma applicators is disposed within the showerhead, wherein one plasma applicator of the plurality of plasma applicators corresponds to one of the plurality of perforated gas diffusion members. Further, a DC bias power source is coupled to a substrate support assembly.

Film stress control for plasma enhanced chemical vapor deposition

Disclosed herein is a device including a driving thin film transistor. The driving thin film transistor includes a metal oxide channel, a source electrode in contact with the driving metal oxide channel, and a top gate electrode disposed above the metal oxide channel and physically connected to the driving source electrode.

Thin film transistors for circuits for use in display devices

Embodiments herein include thin-film transistors (TFTs) including channel layer stacks with layers having differing mobilities. The TFTs disclosed herein transport higher total current through both the low mobility and the high mobility channel layers due to higher carrier density in high mobility channel layer and/or the high mobility channel layers, which increases the speed of response of the TFTs. The TFTs further include a gate structure disposed over the channel layer stack. The gate structure includes one or more gate electrodes, and thus the TFTs are top-gate (TG), double-gate (DG), or bottom-gate (BG) TFTs. The channel layer stack includes a plurality of layers with differing mobilities. The layers with differing mobilities confer various benefits to the TFT. The high mobility layer increases the speed of response of the TFT.

Thin-film transistor

Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

Plasma treatment on metal-oxide TFT

Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

High-K dielectric materials comprising zirconium oxide utilized in display devices

A diffuser includes a front-side gradient surface formed from a diffuser block, a back-side gradient surface formed from the diffuser block, and opening structures formed from the front-side gradient surface to the back-side gradient surface. Each opening structure includes a conical opening having a first end along the front-side gradient surface and a second end corresponding to an apex at a depth within the diffuser block, and a cylindrical opening formed from the depth to the back-side gradient surface. The opening structures are arranged in rows including a first set of rows and a second set of rows alternately positioned along a length of the diffuser block.

Deposition chamber system diffuser with increased power efficiency

Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, a passivation film stack is provided and includes a silicon oxide layer disposed on a workpiece, a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, and a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer. The hydrogen-rich silicon nitride layer has a greater hydrogen concentration than the nitrogen-rich silicon nitride layer.

Nitrogen-rich silicon nitride films for thin film transistors

Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

Hybrid high-K dielectric material film stacks comprising zirconium oxide utilized in display devices

In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual high-k dielectric material formed on one or more interior surfaces of the processing chamber. The reactive species is formed from a halogen-containing gas mixture and the one or more interior surfaces include at least one surface having a coating material formed thereon. The method further comprises reacting the residual high-k dielectric material with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber. The removal rate of the residual high-k dielectric material is greater than a removal rate of the coating material. The high-k dielectric material is selected from zirconium dioxide (ZrO) and hafnium dioxide (HfO). The coating material includes a compound selected from alumina (AlO), yttrium-containing compounds, and combinations thereof.

Selective in-situ cleaning of high-k films from processing chamber using reactive gas precursor

Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrodeis disposed over the gate dielectric layer. The gate dielectric layer has a Dof about 5ecmeVto about 5ecmeVand a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

Process to reduce plasma induced damage

Disclosed herein is a sub-pixel circuit for a display device. The sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

Thin film transistor with small storage capacitor with metal oxide switch

The present disclosure relates to a gas confiner assembly designed to reduce the non-uniform deposition rates by confining the gas flow and changing the local gas flow distribution near the edge regions of the substrate. The material, size, shape and other features of the gas confiner assembly can be varied based on the processing requirements and associated deposition rates. In one embodiment, a gas confiner assembly for a processing chamber comprises a gas confiner configured to decrease gas flow and compensate for high deposition rates on edge regions of substrates. The gas confiner assembly also comprises a cover disposed below the gas confiner. The cover is configured to prevent a substrate support from being exposed to plasma.

Gas confiner assembly for eliminating shadow frame

A method of encapsulating an organic light emitting diode (OLED) is provided. The method includes generating a first plasma in a process chamber, the first plasma having an electron density of at least 10cmwhen an OLED device is positioned within the process chamber. The OLED device includes a substrate and an OLED formed on the substrate. The method further includes pretreating one or more surfaces of the OLED and substrate with the first plasma; depositing a first barrier layer comprising silicon and nitrogen over the OLED by generating a second plasma comprising silicon and nitrogen in the process chamber, the second plasma having an electron density of at least 10cm, and depositing a buffer layer over the first barrier layer; and depositing a second barrier layer comprising silicon and nitrogen over the buffer layer by generating a third plasma comprising silicon and nitrogen in the process chamber.

Thin-film encapsulation

Growing community of inventors

Fremont, CA, United States of America

Soo Young Choi