Samsung Electronics Co., Ltd.

Soo-woong Lee

Dae-Woong Kim

Jung-sung Hwang

Hyung-seok Choi

Sung-hwan Choi

Jin-Hong Kim

Seung-Mok Shin

Il-kwon Kim

Tae-hyeon Sim

A wafer transfer system, and method of controlling pressure in the system, includes a loadport for receiving a wafer container, a housing operably connected to the loadport, a wafer transfer mechanism for transferring a wafer between the wafer container and the housing, a wafer container sensor for detecting a presence of the wafer container on the loadport, a variable speed fan disposed in a first portion of the housing, a variable exhaust unit disposed in a second portion of the housing facing the first portion, the variable exhaust unit being capable of varying an exhaust rate of air from the housing, and a controller for variably operating the variable speed fan and the variable exhaust unit in response to a signal from the wafer container sensor.

Method of controlling pressure in a wafer transfer system

Provided are a restoration system and method for an optical disc, by which a radio frequency signal optically picked up from an optical disc is restored. The restoration system includes a slice, a phase locked loop, a latch circuit, a 3T correction circuit, and a demodulator. In particular, the 3T correction circuit includes an extension storage device, a length measuring device, a phase detector, and an extension determiner and corrects data output from the extension storage device. In the restoration method, data required for determining the need for correction and the direction of correction is detected and a plurality of steps for selecting non-correction, two directional correction, forward correction, and backward correction are performed, thereby correcting the high radio frequency signal according to conditions of the high radio frequency signal. It is preferable that the restoration system operates according to the restoration method.

System and method for restoring an optical disc signal

Wafer transfer system

According to example embodiments of the present invention, there are provided an electrical node of a transistor and a method of forming the same, which may reduce or minimize current leakage between the electrical node and a semiconductor substrate when a buried contact hole exposing at least the side of an active region is arranged on the semiconductor substrate. Two gate patterns may be formed on the active region of the semiconductor substrate. Conductive layer patterns may be formed in the gate patterns and in the semiconductor substrate between the gate patterns. A buried interlayer insulating layer may be formed on the semiconductor substrate to cover the gate patterns. A buried contact hole which passes through the buried interlayer insulating layer and exposes the conductive layer pattern of the semiconductor substrate may be formed. The buried contact hole may be formed to expose at least the side of the active region. An impurity region may be formed in the semiconductor substrate below the buried contact hole. A contact hole spacer covering the sidewall of the buried contact hole may be formed. A buried conductive layer which covers the contact hole spacer and fills the buried contact hole may be formed.

Electrical node of transistor and method of forming the same

A frame synchronization signal detection apparatus includes a synchronization signal detector, a main frame synchronization signal generator, a sub frame synchronization signal generator, and an output unit. The synchronization signal detector detects and outputs a synchronization signal from a digital data signal. The main frame synchronization signal generator detects and outputs a first valid synchronization signal from the synchronization signal, as an internal frame synchronization signal, and generates and outputs a first insertion synchronization signal, as the internal frame synchronization signal, if the first valid synchronization signal is not detected in a predetermined first time period. The sub frame synchronization signal generator detects and outputs a second valid synchronization signal from a synchronization signal. The output unit outputs a frame synchronization signal. The main frame synchronization signal generator stops generating the first insertion synchronization signal, and detects and outputs a first valid synchronization signal as an internal frame synchronization signal.

Apparatus and method for detecting frame synchronization signal for reducing errors in data demodulation in optical disc system

An apparatus and a method for scrambling and descrambling data wordwise in an optical disk system are provided. The apparatus includes a bit storing means which stores at least 15 bits, and a calculating means which calculates first through fifteenth bits of the bit storing means in parallel during one clock cycle and inputs the results of the calculation back into the bit storing means. The calculating means performs an XOR logic operation on a seventh bit and a fifteenth bit, on a first bit, an eighth bit, and a twelfth bit, on a second bit, a ninth bit, and a thirteenth bit, on a third bit, a tenth bit, and a fourteenth bit, on a fourth bit, an eleventh bit, and a fifteenth bit, on the first bit and a fifth bit, on the second bit and a sixth bit, on a third bit and the seventh bit, on the fourth bit and the eighth bit, on the fifth bit and the ninth bit, on the sixth bit and the tenth bit, on the seventh bit and the eleventh bit, on the eighth bit and the twelfth bit, on the ninth bit and the thirteenth bit, and on the tenth bit and the fourteenth bit, and inputs the results of the XOR logic operations into the bit storing means.

Apparatus and method for scrambling and descrambling data wordwise in optical disk system

An optical disc reproducing apparatus including a viterbi detector for an optical disc in which digital data is stored includes an optical pick-up for reading digital data stored in the optical disc and for generating a high frequency signal, an analog-to-digital converter for sampling and quantizing the high frequency signal, and a viterbi detector for decoding a quantized signal output from the analog-to digital converter and reproducing an eight to fourteen modulation (EFM)/EFM&plus;signal. The viterbi detector includes a branch metric calculator for receiving a signal constituted of n bits, for comparing the signal with previously set three variables, and for calculating a branch metric with respect to the input signal. A path metric update and storage unit receives the branch metric, adds the branch metric to values stored therein, compares the error content of all the possible paths with each other, and stores a metric with respect to the path having the smallest amount of errors. A path memory receives the output signal of the path metric update and storage unit and generates a viterbi decoded recovery signal. A stable eight to fourteen modulation (EFM)/EFM&plus;signal is reproduced.

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Suwon-si, South Korea

Soo-woong Lee