Samsung Electronics Co., Ltd.

Other

Korea University Research and Business Foundation

Korea University Industrial Academic Collaboration Foundation

Soo-Won Kim

Ki-hong Kim

Gil-Su Kim

Woo-Jin Rim

Yong-Bae Dhong

Goang-seog Choi

Min-su Jeong

Myoung-Su Song

Young-Jae Min

Kyu-Young Kim

Woo-Kwan Lee

A circuit for correcting a duty-cycle comprises a duty-cycle adjuster for changing a duty-rate of an input clock signal according to a duty control signal; a duty-cycle detector for detecting a duty-rate of an output clock signal based on the input clock signal and the output clock signal from the duty-cycle adjuster; and an algorithm-based digital controller for performing an algorithm according to a duty-rate detection signal outputted from the duty-cycle detector to generate the duty control signal.

High-speed duty cycle correction circuit

A programmable frequency divider, which is a core module of a frequency synthesizer using a Phase Locked Loop (PLL) for generating very high frequencies, includes a divided clock generator dividing a frequency of an input clock signal Fby a first divide ratio (N+1) or a second divide ratio N according to a divide ratio control signal MC to generate a plurality of divided clock signals D; a counting unit counting the number CNT of the plurality of divided clock signals D, by performing swallow mode counting and program mode counting sequentially on the plurality of divided clock signal D; a control signal generator generating the divide ratio control signal MC, using the number CNT of the plurality of divided clock signal D, a count S by the swallow mode counting and a count P by the program mode counting, the count P corresponding to a maximum of the number CNT, feeding the divide ratio control signal MC back to the divided clock generator, and generating a reset control signal RST for resetting the counting unit.

Programmable frequency divider and frequency dividing method thereof

In a data transmitter, a main line driver circuit transmits an input signal to a receiver via a channel. A pre-emphasis circuit emphasizes a voltage level of the transmitted input signal, and a pre-emphasis controller controls the pre-emphasis circuit. The pre-emphasis controller adjusts a pre-emphasis level of the pre-emphasis circuit to increase an amount of current supplied to the channel at a transition time of the input signal in accordance with the transition condition of the channel.

Data transmitters and methods thereof

A pre-decoder applied to a turbo decoder for decoding a punctured turbo code. The turbo code consists of a data bit stream and a plurality of parity bit streams, parts of which are punctured. The pre-decoder has an arithmetic unit for calculating estimated parity bit streams by carrying out, with respect to the data bit stream, the same algorithm used by a turbo encoder to produce the parity bit streams, a comparison unit for comparing the plurality of parity bit streams with the estimated parity bit streams, and a recovery unit for substituting estimated parity symbols for corresponding punctured parts of the parity symbol streams when related non-punctured bits of the parity bit streams are identical with corresponding estimated non-punctured parity bits. The punctured parity symbols are recovered by the pre-decoder completely, or at least partially, and provided to the turbo decoder. Accordingly, the decoding performance of the turbo decoder is enhanced.

Pre-decoder for a turbo decoder, for recovering punctured parity symbols, and a method for recovering a turbo code

A high-speed D flip-flop includes first and second precharge circuits, and first to fifth switching circuits. The first precharge circuit precharges first and second internal nodes to a first supply voltage in response to a clock signal, and the first switching circuit provides a first discharge path between the first internal node and a third internal node in response to an input signal. The second switching circuit provides a second discharge path between the second and third internal nodes in response to a potential of the first internal node, and the second precharge circuit precharges an output terminal to a first supply voltage in response to a potential of the second internal node. The first switching circuit provides a third discharge path between the output terminal an the third internal node in response to the potential of the second internal node, and the fourth switching circuit connects the first to third discharge paths with a second supply voltage in response to the clock signal.

High-speed discharge-suppressed D flip-flop

An analog/digital cable TV (CATV) includes an analog broadcast signal processor for receiving only a signal of a particular channel selected by a user and restoring an analog video signal and an analog audio signal contained in the received analog signal. Also, the CATV includes a digital broadcast signal processor for NTSC-encoding and audio-digital-to-analog-converting the received digital video and audio signals contained in the digital broadcast signal received via a phone jack to then be output to an output signal selector, and outputting the upstream signal via the phone jack connected with a CATV broadcast station. The output signal selector selectively applies the signals output from the digital and analog broadcast signal processors to a monitor. The monitor video-displays and audio-outputs the video and audio data contained in the signal received from the output signal selector. A controller controls the operations of the analog broadcast signal processor, the digital broadcast signal processor and output signal selector.

Analog/digital cable TV capable of performing bidirectional communication

A resolution enhancement apparatus and method of a laser printer using a modulated laser beam is adapted to an image forming apparatus of the laser printer. It includes a memory for storing sequentially input image data in a sequential scanning method, rearranging a scanning line order and generating a 5.times.5 sample window. Also included are a first processor for classifying and outputting a pattern of the image data according to bitmap information in a pixel using nine 3.times.3 masks produced from the 5.times.5 sample window supplied from the memory, a second processor for using pixel density to classify data output from the first processor into a plurality of groups and outputting data of the classified groups, and a signal modulator for modulating data output from the second processor into a predetermined pattern and outputting the modulated pattern. This minimizes the use of memory space by using four row line memories and enhancing resolution by expressing finite shapes according to nineteen modulation patterns while eliminating the more severe portions of pixel magnitude variation (step phenomenon).

Growing community of inventors

Seoul, South Korea

Soo-Won Kim