Samsung Electronics Co., Ltd.

Fairchild Korea Semiconductor Ltd.

Trinno Technology Co., Ltd.

Soo-Seong Kim

Sang-yong Lee

Jun-soo Kim

Chong-man Yun

Kwang-Hoon Oh

Byoung-Ho Choo

Chong Man Yun

Young-dae Kwon

A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.

MOS gate power semiconductor device with anode of protection diode connected to collector electrode

An insulated gate bipolar transistor having a high breakdown voltage in a reverse blocking mode and a method for fabricating the same are provided. The insulated gate bipolar transistor includes a relatively low-concentration lower buffer layer and a relatively high-concentration upper buffer layer. The low-concentration lower buffer layer contacts a semiconductor substrate having a high concentration of first conductivity type impurities used as a collector region, and the high-concentration upper buffer layer contacts a drift region of a second conductivity type. The conductivity type of the upper buffer layer is second conductivity type impurities, and the conductivity type of the lower buffer layer is substantially intrinsic, or first conductivity type impurities, or second conductivity type impurities. According to the present invention, due to the high-concentration upper buffer layer, the thickness of the drift region can be reduced, and during a forward continuity, a switching speed can be improved. Simultaneously, due the low-concentration lower buffer layer, the breakdown voltage of a device can be increased in a reverse blocking mode.

Insulated gate bipolar transistor having high breakdown voltage in reverse blocking mode

A bipolar junction transistor includes a semiconductor substrate having a surface, a base region of first conductivity type in the substrate, and an emitter region of second conductivity type extending from the surface into the base region to form a generally concave semiconductor junction having an apex oriented towards the surface. The emitter region preferably includes a plurality of contiguous emitter subregions extending from the surface into the base region in an arcuate manner and merging to form the generally concave semiconductor junction. The transistor preferably includes an emitter terminal electrically contacting the emitter region at an emitter contact area on the surface, the emitter contact area having a central portion substantially centered with respect to the apex of the semiconductor junction. To produce the bipolar junction transistor, a base layer of first conductivity type is provided in a semiconductor substrate, ions of second conductivity type implanted through the base layer surface in portions of the base layer surface increasing in area from a central portion of the base layer surface laterally towards outer portions of the base layer surface, and the implanted ions diffused into the base layer to thereby create the emitter region and the concave semiconductor junction. Preferably, the ions are implanted by depositing an oxide or other masking layer on the base layer, selectively etching the masking layer to expose the plurality of surface portions, and then implanting the ions into the exposed surface portions.

Methods of fabricating bipolar junction transistors having an increased

An insulated gate semiconductor device includes a relatively highly doped epitaxial JFET region. The epitaxial JFET region forms a P-N junction with the base region of the device, but is spaced from the insulated gate electrode by a more lightly doped epitaxial accumulation region. The use of a spaced JFET region provides a number of important performance advantages over prior art power MOSFETs or IGBTs. By spacing the highly doped JFET region from the top face, the devices of the present invention are, among other things, capable of sustaining higher breakdown voltages without a significant increase in forward on-state resistance. For example, by using a more lightly doped accumulation region underneath the gate electrode, in place of a more highly doped JFET region, the punch-through voltage of the device is increased and electric field crowding at the base junction at the top of the face is decreased. In contrast to those JFET regions in the prior art which are formed by performing a high dose implant and/or high dose diffusion of first conductivity type dopants, the devices according to the present invention reduce the adverse influences on threshold voltage caused by high dose implants of ions adjacent the periphery of the base regions.

Methods of forming insulated gate semiconductor devices having spaced

Bipolar junction transistors having an increased safe operating area

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Seoul, South Korea

Soo-Seong Kim