Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Other

Soo-Min Lee

Byung-Ryul Ryum

Deok-Ho Cho

Tae-Hyeon Han

Kwang-Eui Pyun

Jin-Young Kang

Seong-Hearn Lee

Oh-joon Kwon

The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Method for fabricating of super self-aligned bipolar transistor

The present invention provides a collector device in a bipolar device, having a lateral collector structure on a buried oxide layer. This collector has a high breakdown voltage for high power and operating at a high speed, by isolating a horizontal collector from a substrate by a buried oxide film and horizontally connecting a buried collector to a collector. The buried collector film is formed on the buried insulating film, surrounding the collector film and being horizontally connected to the collector film.

Method for fabricating a lateral collector structure on a buried oxide

The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the problems, such as the punch-through caused by the short distance between the source region and the drain region, the decrease of the breakdown voltage between the source region and the drain region and the leakage current flowing into the bulk region beneath the channel due to the drain-induced barrier lowering. Furthermore, because the source region and the drain region are isolated from the semiconductor substrate by the lower insulation layer, the removal of the parasite junction capacitor speed up the transistor.

Si/SiGe MOSFET and method for fabricating the same

Super self-aligned bipolar transistor

Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxide film and the silicon oxide film and removing the polysilicon film only the inactive region; performing a thermal oxidation to form a field oxide film on the inactive region; and sequentially removing the isolating layer and the polysilicon film formed on the active region. Because the active region is defined using an insulator-filled shallow trench before performing thermal oxidation, no oxygen is penetrated into the active region during the thermal oxidation, whereby a field oxide film can be formed without occurrence of a Bird's beak.

Method for fabricating field oxide isolation region for semiconductor

An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the base electrode polysilicon layer on the shallow trench, and forming a self-aligned base.

Method for fabricating heterojunction bipolar transistor

Method for fabricating semiconductor device isolation region using a

The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth and a polycide base electrode without using a trench for isolating between elements, thereby enhancing the performance thereof, which comprises the steps of: forming sequently a first oxidation film, an electrically conducting thin film and a second oxidation film on top of a substrate; patterning the second oxidation film and the conducting thin film to form a preliminary spacer; removing an exposed portion of the first oxidation film, and selectively growing a collector layer; oxidizing the collector layer to form a thermal oxidation film, and removing the preliminary spacer; depositing a polysilicon and forming a silicon oxidation film and a polysilicon spacer on the second oxidation film and the removed portion of the preliminary spacer, respectively; exposing the base thin film, the spacer and the collector layer to form a SiGe/Si layer; forming a base electrode on the SiGe/Si layer; exposing a portion of the first oxidation film and forming a third oxidation film; exposing a surface of the SiGe/Si layer and forming a oxidation spacer on sides of an etched portion, then self-aligning the emitter and the emitter electrode; and performing a metal wiring process.

Method for manufacturing a super self-aligned bipolar transistor

A silicon/silicon-germanium bipolar transistor fabrication method employs a metallic silicide film as an extrinsic base electrode to reduce resistance of the extrinsic base electrode, and to increase a maximum oscillation frequency and cut-off frequency due to its self-aligned structure. The fabrication method enables agglomeration to occur on the side wall of the polycrystalline silicon film connected to the metallic silicide film instead of on the interface between the metallic silicide film and the lower silicon/silicon-germanium film, and leads the extrinsic base electrode to be sandwitched by the insulator films, thereby realizing a constant resistance and also resulting in the application of integrated circuits to a mass production mechanism.

Silicon-silicon-germanium heterojunction bipolar transistor fabrication

Disclosed is a fabrication of a bipolar transistor using an enhanced trench isolation so as to improve integration and performance thereof, comprising the steps of sequentially etching back portions corresponding to a trench using a trench forming mask to a predetermined depth of the buried collector to form the trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a second nitride layer; etching back layers formed on a portion of the first insulating layer to form an opening in the active region; forming a first side wall on both edges of the opening and removing the first insulating layer; forming an intrinsic base at a region where the first insulating layer is removed to electrically connect the intrinsic base with an extrinsic base in self-alignment; forming a second side wall on both sides of the first side wall; and forming an emitter layer on the intrinsic base.

Method for making bipolar transistor having an enhanced trench isolation

Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer on both sides of the base and the silicon oxide to define an emitter region; forming an emitter on the base; and forming electrodes thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.

Method for fabricating bipolar transistor

Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is fully reduced by using a metallic silicide as a base, comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region; growing a collector epitaxial layer on the buried collector region and forming a field oxide layer; selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer and an first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film thereon to form a base electrode thin film; forming a capping oxide layer of about 500 .ANG. thickness only on the base electrode thin film; forming an isolating oxide layer thereon and sequentially and selectively removing the isolating oxide layer, the capping oxide layer, the base electrode thin film and the base layer using a patterned photomask to form a pattern, the isolating oxide layer being provided to electrically isolate base and emitter; forming a side wall oxide layer at both side edges of the pattern; removing a portion of the isolating oxide layer to define an emitter region; forming a passivation layer thereon and selectively removing the passivation layer to form contact holes; and depositing a polysilicon layer doped with impurity ions in the contact holes to form electrodes.

Method for fabricating hetero-junction bipolar transistor having reduced

Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.

Growing community of inventors

Daejeon, South Korea

Soo-Min Lee