Samsung Electronics Co., Ltd.

Korea Advanced Institute of Science and Technology

Seoul National University

Snu Rdb Foundation

Soo-Jung Ryu

Woong Seo

Yeon-Gon Cho

Young-chul Cho

Ho-Young Kim

Moo-Kyoung Chung

Il-hyun Park

Dong-Hoon Yoo

John Dongjun Kim

Bernhard Egger

Yoon-Jin Kim

Tae-Wook Oh

Seok-Woo Song

Min-Seok Lee

Jeong-Wook Kim

Jaejin Lee

Sang-Heon Lee

Jin-Seok Lee

Seong-Hoon Jeong

Do-Hyun Kim

Jae-Young Kim

Jin-Hoo Lee

Hee Seok Kim

Jeong-joon Yoo

Sundeep Krishnadasan

Jung-Keun Park

Jae-Don Lee

Han-Joon Kim

Choon-Ki Jang

Sung-Bae Park

Hee-jun Shim

Yen-Jo Han

Yeong-gil Shin

Young-Chul Cho

Hong-seok Kim

Seung-Hun Jin

Chang-Moo Kim

Krishnadasan Sundeep

Key-Young Choi

Byeong-Hun Lee

Jun-Kyoung Kim

Jeong-Joon Yoo

Il-Hyun Park

Keun-Soo Yim

Young-Sam Shin

A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.

Processing device and a swizzle pattern generator

A texture processing method and apparatus that obtains information about a first data loss amount that occurred during a texture compression process. A determination is made regarding a second data loss amount that allowable during a texture filtering process based on the obtained information regarding the first data loss amount. Texture filtering is then performed by using the second data loss amount. At least one processor determines the second data loss amount based on a difference between the third data loss amount and the first data loss amount.

Texture processing method and device

An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.

Job scheduling optimization based on ratio of stall to active cycles

A method of processing a graphics pipeline in a graphics processing apparatus includes performing pixel shading to process pixels corresponding to an object, texturing the object, and transmitting data of a textured object to a processing path for a post-processing operation of the textured object. A graphics processing apparatus for processing a graphics pipeline includes a shading processor configured to perform pixel shading to process pixels corresponding to an object. A texturing processor is configured apply to texture the object, determine a post-processing operation mode to adjust visual effects of the textured object, and transmit data of the textured object to a processing path for the post-processing operation in accordance with the determined post-processing mode. A reorder buffer is configured to buffer data of the object in accordance with a processing order when the processing path bypasses the shading processor.

Graphics processing apparatus and method of processing graphics pipeline thereof

Provided is a method of rendering a curve. The method includes determining a tessellation level of dividing a curve based on a control point of the curve, generating at least one triangle and at least two first sub-curves corresponding to the curve based on the tessellation level, and rendering the at least two first sub-curves and the at least one triangle.

Method and apparatus for rendering curve

Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.

Processor and method for dynamically allocating processing elements to front end units using a plurality of registers

A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.

Method and apparatus for generating test bench for verification of processor decoder

The present examples relate to prefetching, and to a cache control device for prefetching and a prefetching method using the cache control device, wherein the cache control device analyzes a memory access pattern of program code, inserts, into the program code, a prefetching command generated by encoding the analyzed access pattern, and executes the prefetching command inserted into the program code in order to prefetch data into a cache, thereby maximizing prefetching efficiency.

Cache control device for prefetching  using pattern analysis processor and prefetch instruction and prefetching method using cache control device

A functional unit for supporting multithreading, a processor including the same, and an operating method of the processor are provided. The functional unit for supporting multithreading includes a plurality of input ports configured to receive opcodes and operands for a plurality of threads, wherein each of the plurality of input ports is configured to receive an opcode and an operand for a different thread, a plurality of operators configured to perform operations using the received operands, an operator selector configured to select, based on each opcode, an operator from among the plurality of operators to perform a specific operation using an operand from among the received operands, and a plurality of output ports configured to output operation results of operations for each thread.

Functional unit for supporting multithreading, processor comprising the same, and operating method thereof

A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory, when the shared memory and each of the processors is configured to generate a delayed signal, includes a delayed signal detector configured to detect the generated delayed signal; and one or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal.

Latency management system and method for multiprocessor system

Provided is a processor with a data transfer structure that is excellent in performance and efficiency. According to an aspect, the processor may include a plurality of processing elements, a plurality of routers respectively connected to the processing elements, and a plurality of connection links formed between the routers such that data is transferred between the processors via a network.

Coarse-grained reconfigurable array based on a static router

A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores.

Multi-core apparatus and job scheduling method thereof

A coarse-grained reconfigurable processor having an improved code compression rate and a code decompression method thereof are provided to reduce a capacity of a configuration memory and reduce power consumption in a processor chip. The coarse-grained reconfigurable processor includes a configuration memory configured to store reconfiguration information including a header storing a compression mode indicator and a compressed code for each of a plurality of units and a body storing at least one uncompressed code, a decompressor configured to specify a code corresponding to each of the plurality of units among the at least one uncompressed code within the body based on the compression mode indicator and the compressed code within the header, and a reconfigurator including a plurality of PEs and configured to reconfigure data paths of the plurality of PEs based on the code corresponding to each unit.

Coarse-grained reconfigurable processor and code decompression method thereof

Growing community of inventors

Hwaseong-si, South Korea

Soo-Jung Ryu