Sumitomo Electric Industries, Limited

Massachusetts Institute of Technology

Agency for Science, Technology and Research

National University of Singapore

Nanyang Technological University

Institute of Materials Research and Engineering

Soo-Jin Chua

Jurgen Michel

Li Hong Zhang

Eiryo Takasuka

Peng Chen

Eng Kian Kenneth Lee

Li-Shiuan Peh

Siau Ben Chiah

Bing Wang

Wenjia Zhang

Zhaomin Zhu

Wei Wang

Masaki Ueno

Fan Zhou

Zhen Chen

Zhi-Jie Wang

A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.

Method of forming an integrated circuit and related integrated circuit

A method () of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing () the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding () at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.

A white-light emitting diode comprises an n-type semiconductor layer, one or more quantum well structures formed over the n-type semiconductor layer, a p-type semiconductor layer formed on the quantum well structure, a first electrode formed on the p-type semiconductor, and a second electrode formed on at least a portion of the n-type semiconductor layer. Each quantum well structure includes an InGaN quantum well layer, an InGaN barrier layer (x&#x3e;0.3 or x=0.3), and InGaN quantum dots, where x&#x3c;y&#x3c;z&#x2266;1.

Group III nitride white light emitting diode

The GaN single-crystal substratein accordance with the present invention has a polished surface subjected to heat treatment for at least 10 minutes at a substrate temperature of at least 1020&#xb0; C. in a mixed gas atmosphere containing at least an NHgas. As a consequence, an atomic rearrangement is effected in the surface of the substratein which a large number of minute defects are formed by polishing, so as to flatten the surface of the substrateTherefore, the surface of an epitaxial layerformed on the substratecan be made flat.

GaN single-crystal substrate, nitride type semiconductor epitaxial substrate, nitride type semiconductor device, and methods of making the same

A method of manufacturing a semiconductor optical device comprising the steps of: providing a substrate having an active layer thereon; providing an aluminium-bearing layer, the aluminium bearing layer being adjacent the active layer; and oxidising the aluminium-bearing layer substantially entirely.

Buried hetero-structure opto-electronic device

Growing community of inventors

Singapore, Singapore

Soo-Jin Chua