Samsung Electronics Co., Ltd.

Soo-Ho Cha

Chankyung Kim

Sungchul Park

Kwangchol Choe

Dong-seok Kang

Chul-woo Park

Hye-Jin Kim

Sang-beom Kang

Chan-Kyung Kim

Yun-sang Lee

Dong-hyun Sohn

Hoyoung Song

Hyung-rock Oh

Seongil O

Yunsang Lee

Disclosed is a memory device which includes a first memory cell connected to a word line and a first bit line, a second memory cell connected to the word line and a second bit line, and a row decoder selecting the word line, a row decoder configured to select the word line, and a column decoder. A first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell. The column decoder selects the first bit line based on a time point when the first memory cell is activated.

Memory device with improved latency and operating method thereof

Memory devices may include a memory cell connected to a word line and a bit line, a first bit line sense amplifier connected to the memory cell through the bit line and configured to amplify a signal of the bit line, and a second bit line sense amplifier disposed adjacent to the first bit line sense amplifier and not connected to the bit line. The second bit line sense amplifier may be selected by an address received from a processor, and data may be stored in the second bit line sense amplifier or the data is output from the second bit line sense amplifier according to a command received from the processor. In some aspects described herein, the memory device may include a buffer memory that operates at high speed, thereby increasing performance of a memory module.

Memory device using sense amplifiers as buffer memory with reduced access time and method of cache operation of the same

Disclosed are a memory device, a memory package including the same, and a memory module including the same. The memory package includes a first memory device configured to operate in response to a first chip select signal from an external device, a second memory device configured to operate in response to a second chip select signal from the external device, and a third memory device configured to operate in response to a third chip select signal from the external device. The third memory device includes a buffer unit that is connected with an internal circuit of the third memory device through an internal data line, is connected with the first memory device through a first memory data line, is connected with the second memory device through a second memory data line, and is connected with the external device through a data line.

Memory device, memory package including the same, and memory module including the same

A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

Spin transfer torque magnetic random access memory for supporting operational modes with mode register

A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.

Memory device including memory cell for generating reference voltage

Disclosed is a current sense amplifier suitable for a nonvolatile memory device such as a magnetic random access memory. In the current sense amplifier, a reference memory cell for sensing is implemented by a memory cell equal to a normal memory cell without fabricating different reference memory cells. The current sense amplifier is formed of first and second cross coupled differential amplifiers being covalent bonded. The current sense amplifier compares a current flowing to a sensing node of a memory cell directly with currents flowing to reference sensing nodes.

Current sense amplifying circuit in semiconductor memory device

A data reading method of a magnetic memory device includes generating read commands, supplying a read current to a selected magnetic memory element in a first direction and in turn in a second direction under different ones of the read commands, respectively, and sensing the magnitude of the read current flowing through the selected magnetic memory element to read data stored at the selected magnetic memory element.

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Seoul, South Korea

Soo-Ho Cha