Samsung Electronics Co., Ltd.

Soo-hee Park

Yoon-tae Lee

Jin-sil Kim

An image forming apparatus including: a communication interface unit to receive print data; an image processing unit to convert the received print data into pages of bitmap image data; an image forming unit to print the pages and having a queuing time; and a queuing time changing unit to change the queuing time according to a conversion time of the print data by the image processing unit.

Image forming apparatus and method of forming an image thereof

An image forming apparatus including a multi-processor and an image forming method thereof. The apparatus includes a data processing unit to divide input print data into a plurality of divided print data according to a predetermined criterion and to simultaneously process the plurality of divided print data using a multi-processor, and an image forming unit to form an image corresponding to the processed print data.

Image forming apparatus and method using multi-processor

An image forming apparatus including a chip having an engine processor and a basic processor includes an image forming unit which has an image forming engine and forms an image of given image data, an engine processor to control a driving of the image forming engine, and a basic processor which is integrally provided with the engine processor and controls processes related to image formation except the driving of the image forming engine.

Image forming apparatus including chip having engine processor and basic processor

Provided are a method and apparatus for reducing the number of power ports equipped with an integrated circuit (IC) apparatus by reducing the number of bus outputs that are simultaneously switched, with the use of a master clock signal and a slave clock signal, which is a variation of the master clock signal. The IC apparatus includes a slave clock signal generator, which receives the master clock signal and generates a slave clock signal for controlling simultaneously switching outputs; and a flipflop circuit, which transmits a signal to an external device in synchronization with the slave clock signal.

Method and integrated circuit apparatus for reducing simultaneously switching output

A refresh controlling method and a refresh controlling apparatus includes a count initialization value setting unit to set a count initialization value at an initial refresh interval or a changed refresh interval, and a bus request signal generation unit to generate a bus request signal when the count initialization value is completely lapsed. The apparatus also includes a refresh signal generator generate a refresh signal when a bus approval signal is generated by detection of a bus blank period, during which a bus request signal is not received from bus master devices, or when a bus approval signal is generated in response to the bus request signal received from the bus request signal generation unit. According to a logic signal received from the bus request signal generation unit, a bus blank determiner determines whether the bus approval signal has been generated due to the bus blank period. If it is determined that the bus approval signal has been generated due to the bus blank period, the bus blank determiner controls the count initialization value setting unit, the bus request signal generation unit, and the refresh signal generator.

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Suwon-si, South Korea

Soo-hee Park