Samsung Electronics Co., Ltd.

Soo-Han Kim

Jae-Yong Jeong

Ji-Ho Cho

June-Hong Park

Dae Han Kim

A non-volatile memory device including a cell array having memory cells arranged at intersections of word lines and bit lines; an address decoder configured to select one of the word lines in response to an address; a write circuit configured to write program data in memory cells connected with the selected word line; and a control circuit configured to control the address decoder and the write circuit such that a plurality of band program (write) operations are sequentially executed during a write operation, wherein the control circuit is further configured to select each band write operation the optimal write condition of the next band write operation. A plurality of available write conditions are stored as trim information in a plurality of registers. The control circuit selects the register storing information for performing programming under the optimal write condition.

Nonvolatile memory device and memory system having the same

Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a 'passed' memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., &#x394;V) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., &#x394;V) lower than the first step height.

Flash memory devices that support incremental step-pulse programming using nonuniform verify time intervals

A flash memory device includes a memory cell array and a multi-buffer block which temporarily stores program data that are to be stored in the memory cell array, wherein the multi-buffer block includes a plurality of buffer circuits which store at least 2-word data, respectively. Each of the buffer circuits includes a plurality of registers which store two corresponding data bits among the at least 2-word data, respectively and scan logics corresponding to the registers, respectively, which scan a number of program data of a first word data among the at least 2-word data during a first scan interval, and which scan a number of program data of a second word data among the at least 2-word data based on the number of the program data of the first word data during a second scan interval.

Flash memory device including multi-buffer block

Circuit and method for adaptive incremental step-pulse programming in a flash memory device

Exposure equipment adapted for use in the manufacture of semiconductor devices and a related control are disclosed. A wafer stage in the exposure equipment comprises an image sensor adapted to detect patterned light from the reticle. Image data corresponding to the detected patterned light is compared to reference image data to verify a state of overlay mismatch of reticle pattern accuracy prior to wafer exposure.

Growing community of inventors

Hwaseong-si, South Korea

Soo-Han Kim