Samsung Electronics Co., Ltd.

Soo-Geun Lee

Kyoung-woo Lee

Ki-Chul Park

Kyung-Tae Lee

Jeong-Hoon Ahn

Il-Goo Kim

Yong-Jun Lee

Wan-Jae Park

Mu-Kyeng Jung

Hong-Jae Shin

Chul-Sung Kim

Ja-Hum Ku

Jae-hak Kim

Tae-Wook Seo

Eung-joon Lee

Joo-Hyuk Chung

Jae-Hak Kim

Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Integrated circuit capacitor structure

An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

Structure of a CMOS image sensor and method for fabricating the same

Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD method. Treating the silicon oxycarbide layer with plasma is performed by supplying at least one gas selected from a group of He, H, NO, NH, N, Oand Ar. It is desirable that plasma be applied at the silicon oxycarbide layer in a PECVD device by an in situ method after forming the silicon oxycarbide layer. In a case in which a capping layer is further stacked and patterned, it is desirable to treat with H-plasma. Even in a case in which an interlayer insulation is formed of the silicon oxycarbide layer and a coating layer of an organic polymer group for a dual damascene process, it is desirable to perform the plasma treatment before forming the coating layer.

Method of fabricating semiconductor devices having low dielectric interlayer insulation layer

There is provided a semiconductor device fabrication method. In the method, a gate layer is formed on a semiconductor substrate and patterned to form a first resultant structure, a metal layer is formed on the first resultant structure, a capping layer is formed on the metal layer, a metal silicide is formed on the gate layer by heating the substrate at a first temperature, unreacted metal layer and first capping layer are removed to form a second resultant structure, a second capping layer is formed on the second resultant structure, and the substrate is heated at a second temperature higher than the first temperature. The second capping layer suppresses a silicidation rate in the secondary heat treatment, thereby allowing a silicide of a good morphology to be achieved.

Method of forming self-aligned silicide in semiconductor device

Growing community of inventors

Kyung-Gi Do, South Korea

Soo-Geun Lee