Tokyo Electron Limited

Tel Epion Corporation

Soo Doo Chae

Gerrit J Leusink

Noel Russell

Jeffrey Smith

Kai-Hung Yu

Lior Huli

Nicholas Joy

Joshua LaRose

Sang Cheol Han

Robert Daniel Clark

Kandabara N Tapily

David L O'Meara

Kaoru Maekawa

Vincent Lagana-Gizzo

Hojin Kim

Sunghil Lee

Sangcheol Han

Akiteru Ko

Angelique Denise Raley

Toshio Hasegawa

Richard Farrell

Eric Chih-Fang Liu

Youngwoo Park

Steven P Caliendo

Yan Shao

Yoshihiro Kato

Luis Fernandez

Allen J Leith

Satoru Nakamura

Wanjae Park

Vincent Gizzo

Qiaowei Lou

Wan Jae Park

Karthikeyan Pillai

Na Young Bae

Karthik Pillai

Iljung Park

Stephen Mancini

Choong-man Lee

Youngdon Chang

Il-seok Song

Technologies for fabricating a vertical dynamic random access memory (DRAM) structure include forming a DRAM cell hole through a word line layer and an associated substrate such that a first section of the DRAM cell hole extends through the word line layer and a second section of the DRAM cell hole extends through the substrate in vertical alignment with the first section. A pillar capacitor structure is initially formed using the second section of the DRAM cell hole, followed by the formation of a transistor using the first section of the DRAM cell hole as a channel for the transistor. Due to the use of a common DRAM cell hole, the pillar capacitor structure and the channel are in vertical alignment. The substrate is subsequently flipped and removed from the pillar capacitor structure, which is further processed to form a pillar capacitor. In some embodiments, the channel may be formed from a deposition of indium gallium zinc oxide (IGZO).

Technologies for fabricating a vertical DRAM structure

A three-dimensional (3D) memory structure includes a memory array formed on a side of a substrate, a far-back-end-of-line (FBEOL) structure formed on the memory array, and a back-end-of-line (BEOL) structure formed on another side of the substrate opposite the side on which the memory array and the BEOL structure are formed. Methodologies to fabricate the 3D memory structure are also disclosed and include forming the memory array on the substrate, forming the FBEOL on the memory array, flipping the substrate, and forming the BEOL on the opposite side of the substrate. Alternative 3D memory structures and fabrication methodologies are also disclosed.

Technologies for fabricating a 3D memory structure

In certain embodiments, a method of fabricating a device includes forming, on a substrate, a layer stack of alternating layers of a first spin-on material and a second spin-on material. Each layer of the first spin-on material and the second spin-on material is formed by spin-on deposition. The method includes etching first openings through the layer stack and filling the first openings with a third material. The method includes etching second openings through the layer stack, removing the first spin-on material from the layer stack, and replacing the first spin-on material with a fourth material. The fourth material is a first metal-containing material.

Fabricating three-dimensional semiconductor structures

This disclosure describes a method for fabricating a plurality of semiconductor devices in a semiconductor wafer includes: bowing a semiconductor wafer including a substrate by covering the substrate with a strained layer; forming trenches at locations in scribe lines of the semiconductor wafer, the scribe lines identifying areas between adjacent dies on the semiconductor wafer; and reducing the bowing of the semiconductor wafer by filling the trenches with a stress-compensation material.

Stress relief in semiconductor wafers

A method for fabricating a semiconductor device is described that includes forming a base layer over a top layer of a substrate, the base layer includes a silicon based dielectric having a thickness less than or equal to 5 nm and greater than or equal to 0.5 nm; forming a photoresist layer over the base layer, the photoresist including a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer with a pattern of electron flux from the second side, the electron flux being directed into the photoresist layer from the base layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.

Extreme ultraviolet lithography patterning method

Embodiments provide raised pad formations for step contacts in three-dimensional structures formed on microelectronic workpieces. Steps are formed in a multilayer stack that is used for the three-dimensional structure. The multilayer stack includes alternating non-conductive and conductive layers. For one embodiment, alternating oxide and polysilicon layers are used. The steps expose contact regions on different conductive layers. Material layers are formed on the contact regions to form raised pads. The material layers preferably have a high selectivity with respect to the non-conductive material for etch processes. A protective layer is formed over the steps and the raised pads, and contact holes are formed through the protective layer to the raised pads. Contacts are then formed within the contact holes. The raised pads inhibit punch-through of the non-conductive layers during the forming of the contact holes thereby improving performance of resulting devices formed in the microelectronic workpieces.

Raised pad formations for contacts in three-dimensional structures on microelectronic workpieces

Embodiments of methods for patterning using enhancement of surface adhesion are presented. In an embodiment, a method for patterning using enhancement of surface adhesion may include providing an input substrate with an anti-reflective coating layer and an underlying layer. Such a method may also include performing a surface adhesion modification process on the substrate, the surface adhesion modification process utilizing a plasma treatment configured to increase an adhesion property of an anti-reflective coating layer without affecting downstream processes. In an embodiment, the method may also include performing a photoresist coating process, a mask exposure process, and a developing process to generate a target patterned structure in a photoresist layer on the substrate. In such embodiments, the method may include controlling operating parameters of the surface adhesion modification process to achieve target profiles of the patterned structure and substrate throughput objectives.

Plasma treatment method to enhance surface adhesion for lithography

A method of patterning a substrate includes receiving a substrate having microfabricated structures, including mandrels; executing a deposition process that deposits a first material on the mandrels, the deposition process including cyclically moving the substrate through a set of deposition modules. The substrate is moved through the set of deposition modules so that the first material is deposited at a first thickness at top portions of the mandrels and at a second thickness at bottom portions of mandrels, the first thickness being greater than the second thickness. The method includes executing a spacer deposition process that conformally deposits a second material on the substrate; executing a spacer open etch that removes depositions of the second material from over a top surface of the mandrels; removing the first material and the mandrels from the substrate, leaving sidewall spacers; and transferring a pattern defined by the sidewall spacers into an underlying layer.

Deposition process

A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

Interconnect structure and method of forming the same

A method is provided for forming a semiconductor device. The method includes forming a vertical film stack containing a sacrificial layer on a substrate and dielectric layers alternatingly and repeatedly stacked on the sacrificial layer, removing the sacrificial layer to form a horizontal channel above the substrate, depositing a conformal dielectric layer in the horizontal channel, etching trenches in the vertical film stack that connect to the horizontal channel. The method further includes removing the conformal dielectric layer from the horizontal channel, filling the horizontal channel and the trenches with a first electrically conductive material, removing the first electrically conductive material from the trenches, and filling the trenches with a second electrically conductive material.

Method of fabricating semiconductor device

Methods are disclosed that selectively deposit a protective material on the top regions of patterned photoresist layers, such patterned EUV photoresist layers, to provide a protective cap that reduces erosion damage during etch processes used for pattern transfer. Some deposition of the protective material on the sidewalls of the patterned photoresist layer is acceptable, and any deposition of the protective material on the underlying layer below the patterned photoresist layer is preferably thinner than the deposition at the top of the photoresist pattern. Further, the selective deposition of protective caps can be implemented, for example, through the application of high-rotation speeds to spatial atomic layer deposition (ALD) techniques. The selective deposition of protective caps increases the flexibility of options to improve etch resistance for various processes/materials.

Selective atomic layer deposition (ALD) of protective caps to enhance extreme ultra-violet (EUV) etch resistance

A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.

Method of integrated circuit fabrication with dual metal power rail

A substrate processing method for forming a self-aligned contact using selective SiOdeposition is described in various embodiments. The method includes providing a planarized substrate containing a dielectric layer surface and a metal-containing surface, coating the dielectric layer surface with a metal-containing catalyst layer, and exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiOlayer on the metal-containing catalyst layer on the dielectric layer surface. According to one embodiment, the method further includes depositing an etch stop layer on the SiOlayer and on the metal-containing surfaces, depositing an interlayer dielectric layer on the planarized substrate, etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface, and filling the recessed feature with a metal.

Method of forming a self-aligned contact using selective SiOdeposition

A system and method for performing location specific processing of a workpiece is described. The method includes placing a microelectronic workpiece in a beam processing system, selecting a beam scan size for a beam scan pattern that is smaller than a dimension of the microelectronic workpiece, generating a processing beam, and processing a target region of the microelectronic workpiece by irradiating the processing beam along the beam scan pattern onto the target region within the beam scan size selected for processing the microelectronic workpiece.

Method for high throughput using beam scan size and beam position in gas cluster ion beam processing system

Growing community of inventors

Guilderland, NY, United States of America

Soo Doo Chae