Samsung Electronics Co., Ltd.

Soo-cheol Lee

Tae-Jung Lee

Dong-Ryul Chang

Heon-Jong Shin

Jong-hyon Ahn

Hyae-Ryoung Lee

Sang-don Yi

Ho-ik Hwang

Sang-bae Yi

Chang-Hun Lee

Hyun-Sik Kim

Byung-Soo Kim

Hwa-Sook Shin

Yong-Jae Lee

Sung-hoan Kim

Geun-sook Park

Yong Jong Park

Heon-jong Shin

Yun-Seung Shin

Sun-hak Lee

Jong-Hyon Ahn

Mueng-Ryul Lee

Kwang-dong Yoo

Jun-eui Song

Gyeong-Hee Kim

Kyoung-Mok Son

Young-ok Kim

Ki-Jik Lee

Dong-ryul Jang

Kyoung-mok Son

Young-pill Kim

Moo-jin Jung

Jae-Cheol Yoo

Son-jong Wang

Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

Method of fabricating semiconductor integrated circuit device

An electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

EEPROM devices and methods of operating and fabricating the same

A source driver for controlling a slew rate of a liquid crystal display (LCD) and a method for controlling the slew rate is provided. The source driver includes a plurality of output buffers for driving data lines, and a bias circuit for varying a bias voltage inputted to the output buffers to control a slew rate of the output buffers.

Source driver for controlling a slew rate and a method for controlling the slew rate

An output buffer with an improved output deviation and a source driver of a flat panel display which employs the output buffer wherein the output buffer includes a first input terminal to which a first differential input signal is applied, a second input terminal to which a second differential input signal is applied, an output terminal that generates an output signal based on the second differential input signal and feeds back the output signal to the first input terminal as the first input signal, a first power supply terminal to which a first power supply voltage is applied, a second power supply terminal to which a second power supply voltage is applied, and an amplification unit that amplifies a difference between the first differential input signal and the second differential input signal, pulls up the output signal to the first power supply voltage or pulls down the output signal to the second power supply voltage, and includes a plurality of transistors.

Output buffer with improved output deviation and source driver for flat panel display having the output buffer

A semiconductor device includes at least two transistors and a charge-trapping structure. The charge-trapping structure traps charges, which are moved from a selected transistor toward a non-selected transistor, adjacent to the selected transistor among the transistors, thereby preventing a threshold voltage of the non-selected transistor from being increased. Thus, the charge-trapping structure traps the charges so that an increase of the threshold voltage of the non-selected voltage is suppressed.

Semiconductor device and methods of manufacturing the same

A semiconductor device includes a pad electrode layer and an align mark layer, formed on the semiconductor substrate. A passivation layer is formed on the semiconductor substrate and exposes at least a portion of the top of the pad electrode layer and at least a portion of the top of the align mark layer. A light-transmitting protecting layer covers at least a portion of the passivation layer, exposes the top portion of the pad electrode layer exposed from the passivation layer, and covers the portion of the align mark layer exposed from the passivation layer.

Semiconductor device having align mark layer and method of fabricating the same

A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.

Method of fabricating semiconductor device having gate dielectrics with different thicknesses

A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.

Transistor having a protruded drain

Semiconductor integrated circuit device

In a semiconductor device having a dual isolation structure, and a method of fabricating the same, an epitaxial layer is formed on the entire surface of the semiconductor device. A device region including the semiconductor device and the epitaxial layer is defined by a device isolation layer. The device isolation layer has a dual structure that includes a diffused isolation layer and a trench isolation layer. The diffused isolation layer is formed in the semiconductor substrate, and surrounds the base and the bottom sidewall of the device region, and the trench isolation layer surrounds the upper sidewall of the device region by vertically penetrating the epitaxial layer. The method of fabricating a semiconductor device is performed by forming a diffused bottom isolation layer at a predetermined region in the semiconductor substrate, and forming a trench exposed at a predetermined region of the semiconductor substrate by patterning the epitaxial layer formed on the entire surface of the semiconductor substrate. A diffused isolation wall is formed to be connected to the diffused bottom isolation layer under the trench. A trench isolation structure is formed to be connected to the diffused isolation wall by filling an insulating layer inside the trench.

Semiconductor device having dual isolation structure and method of fabricating the same

Metal-insulator-metal integrated circuit capacitors include a pair of metal-insulator-metal capacitors on an integrated circuit substrate that are electronically connected in antiparallel. The pair of metal-insulator-metal capacitors that are electrically connected in antiparallel has less capacitance variation as a function of voltage than either of the metal-insulator-metal capacitors.

Integrated circuit metal-insulator-metal capacitors formed of pairs of capacitors connected in antiparallel

Growing community of inventors

Seoul, South Korea

Soo-cheol Lee