Intel Corporation

Sonja Koller

Georg Seidemann

Andreas Wolter

Bernd Waidhas

Christian Geissler

Sven Albers

Reinhard Mahnkopf

Andreas Augustin

Thorsten Meyer

Klaus Reingruber

Josef Hagn

Thomas Wagner

Kilian Roth

Stephan Stoeckl

Jan Proschwitz

Vishnu Prasad

Hans-Joachim Barth

Sandeep B Sane

Thomas Ort

Shubhada H Sahasrabudhe

Teodora Ossiander

Bastiaan Elshof

Alexandra Atzesdorfer

Present disclosure relates to IC packages with integrated thermal contacts. In some embodiments, an IC package includes a package substrate, an IC die that is coupled to the package substrate, and at least one thermal contact for coupling to at least a portion of a heat exchanger, where the thermal contact is limited to being in a region located at a periphery of the IC package. In some embodiments, thermal contacts are such that at least a portion of a heat exchanger is to be attached on the side of the IC package. In some embodiments, thermal contacts may be provided within a recessed portion at the periphery of the IC package. Providing a thermal contact at a periphery of an IC package may enable improved cooling options, especially for systems where there is no or limited space for providing conventional heat exchangers on the top of the package.

Thermal contacts at periphery of integrated circuit packages

A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.

Printed wiring-board islands for connecting chip packages and methods of assembling same

Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects. The first interconnects may include through-mold vias (TMVs), through-silicon vias (TSVs), conductive sidewalls, or conductive trenches.

Single metal cavity antenna in package connected to an integrated transceiver front-end

A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

Semiconductor packages, and methods for forming semiconductor packages

Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a cavity resonator antenna over the first conductive layer and substrate. The cavity resonator antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the cavity resonator antenna, first conductive layer, and substrate. The conductive cavity may extend vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects. The first interconnects may include through-mold vias (TMVs), through-silicon vias (TSVs), conductive sidewalls, or conductive trenches.

Package integrated cavity resonator antenna

A recess in a die backside surface occupies a footprint that accommodates an inductor coil that is formed in metallization above an active surface of the die. Less semiconductive material is therefore close to the inductor coil. A ferromagnetic material is formed in the recess, or a ferromagnetic material is formed on a dielectric layer above the inductor coil. The recess may extend across a die that allows the die to be deflected at the recess.

Magnetic coils in locally thinned silicon bridges and methods of assembling same

Present disclosure relates to IC devices with thermal mitigation structures in the form of metal structures provided in a semiconductor material of a substrate on which active electronic devices are integrated (i.e., front-end metal structures). In one aspect, an IC device includes a substrate having a first face and a second face, where at least one active electronic device is integrated at the first face of the substrate. The IC device further includes at least one front-end metal structure that extends from the first face of the substrate into the substrate to a depth that is smaller than a distance between the first face and the second face. Providing front-end metal structures may enable improved cooling options because such structures may be placed in closer vicinity to the active electronic devices, compared to conventional thermal mitigation approaches.

Integrated circuit devices with front-end metal structures

A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.

Patch antennas stitched to systems in packages and methods of assembling same

A system-in-package apparatus includes a square wave lead frame that provides a recess for a first semiconductive device as well as a feature for a second device. The system-in-package apparatus includes a printed wiling board that is wrapped onto the lead frame after a manner to enclose the first semiconductive device into the recess.

Lead frame with angular deflections and wrapped printed wiring boards for system-in-package apparatus

A system-in-package apparatus includes a contoured heat sink that provides a first recess and a subsequent recess. The system-in-package apparatus includes a flexible printed wiring board that is wrapped onto the contoured heat sink after a manner to enclose the first semiconductive device into the first recess and a semiconductive device in the subsequent recess.

Contoured-on-heat-sink, wrapped printed wiring boards for system-in-package apparatus

A method for forming a carrier substrate for a semiconductor device, the method includes providing a substrate layer including conductive particles embedded in an electrically insulating material and localized heating of the substrate layer along a desired trace by a laser to form a conductive trace of merged particles along the desired trace.

Carrier substrate for a semiconductor device and a method for forming a carrier substrate for a semiconductor device

An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.

Interposer with conductive routing exposed on sidewalls

A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.

Power mesh-on-die trace bumping

A semiconductor device includes a plurality of circuit regions formed at a circuit semiconductor layer of a semiconductor die. The semiconductor device includes an etch stop layer of the semiconductor die arranged between the circuit semiconductor layer of the semiconductor die and a handling layer of the semiconductor die. The semiconductor device includes one or more trench structures extending through the handling layer of the semiconductor die. The one or more trench structures extends to at least the etch stop layer and to at most the circuit semiconductor layer of the semiconductor die.

Growing community of inventors

Wuppertal, Germany

Sonja Koller