Intel Corporation

Ionq, Inc.

Sonika Johri

Anne Y Matsuura

Justin Hogaboam

Xiang Chris Zou

Adam Holmes

Ravi Pillarisetty

James S Clarke

Thomas Francis Watson

Sahar Daraeizadeh

As system is provided for performing a method of receiving a superposition state defined by a sum of a plurality of addends, wherein each addend of the plurality of addends is a product between a corresponding coefficient of a plurality of coefficients and a corresponding state of a plurality of states encoded with block unary encoding. The system may identify at least one error state, of the plurality of states, having a string value that is not a block unary code string of a set of block unary code strings. The system may compute an updated superposition state based on the plurality of states without the error state.

System and method for error correction in quantum computing

Apparatus and method for a full quantum system simulator. For example, one embodiment of a method comprises: initializing a quantum computing system simulator for simulating multiple layers of a quantum system including one or more non-quantum layers and one or more physical quantum device layers of the quantum system; simulating a first set of operations of the one or more non-quantum layers of the quantum system to generate first simulation results; simulating a second set of operations of the one or more quantum device layers of the quantum system to generate second simulation results; analyzing the first and second simulation results to provide at least one configuration recommendation for the quantum system.

Apparatus and method for quantum computing performance simulation

Apparatus and method for specifying quantum operation parallelism. For example, one embodiment of an apparatus comprises: instruction fetch circuitry to fetch a plurality of quantum instructions from a memory or a cache; slice-based instruction processing circuitry to identify quantum circuit slices comprising sets of one or more of the plurality of quantum instructions; and one or more instruction decoders to decode the quantum instructions to generate quantum microoperations; and quantum execution circuitry to execute sets of the quantum microoperations in parallel based on the quantum circuit slices.

Apparatus and method for specifying quantum operation parallelism for a quantum control processor

Apparatus and method for replacing portions of a quantum circuit with multi-qubit gates. For example, one embodiment of an apparatus comprises: a quantum circuit analyzer to evaluate an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification, the quantum circuit analyzer to generate results of the evaluation; a quantum circuit generator to generate a new quantum circuit specification based on the results of the evaluation generated by the quantum circuit analyzer, the quantum circuit generator to generate the new quantum circuit specification by, at least in part, replacing the one or more sub-circuits of the original quantum circuit specification with one or more multi-qubit gates.

Apparatus and method for quantum performance and/or error correction enhancement using multi-qubit gates

Apparatus and method for dynamically adjusting a quantum computer clock frequency. For example, one embodiment of an apparatus comprises: a quantum execution unit to execute quantum operations specified by a quantum runtime; a qubit drive controller to translate the quantum operations into physical pulses directed to qubits on a quantum chip at a first cycle frequency; a spin echo sequencer to issue spin echo command sequences to cause the qubit drive controller to generate a sequence of spin echo pulses at the first cycle frequency; and qubit measurement circuitry to measure the qubits and to store qubit timing data for each qubit, the qubit timing data indicating a coherence time or an amount of computational time available for each qubit to perform quantum operations.

Apparatus and method for dynamically adjusting quantum computer clock frequency with a locking pulse

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; and a plurality of gates above the quantum well stack, wherein the gates are arranged in a ladder arrangement including two rails having at least N gates each and at least one active rung, and a number of active rungs in the ladder arrangement is less than N.

Growing community of inventors

Portland, OR, United States of America

Sonika Johri