Intel Corporation

Lenovo (singapore) Pte. Ltd.

Songwu Shen

Ned M Smith

Weigang Li

Junyuan Wang

Ziye Yang

Changzheng Wei

Wenqian Yu

Xin Zeng

Douglas Wayne Oliver

Wenwei Tang

Kaijie Guo

Laurent Coquerel

Zijuan Fan

Maksim Lukoshkov

Yao Huo

Nathan K Campbell

ShengRui Ji

Techniques and mechanisms for determining an operation to be performed with a direct memory access (DMA) request. An inspection unit () is coupled between an input-output memory management unit (IOMMU) () and an endpoint device (). The inspection unit () stores a registry () comprising entries () which each correspond to a respective address, and a respective one or more resources of the endpoint device (). A given entry () of the registry () is created based on a message from the IOM MU () which indicates the successful completion of an address translation to facilitate a DMA request. The endpoint device () performs a search, based on a DMA request, to determine if any registry () entry () indicates a combination of an address and an endpoint resource, where said combination matches a corresponding combination indicated by the DMA request. Communication of the DMA request to the IOMMU () is contingent on a result of the search.

Device, system, and method for inspecting direct memory access requests

Technologies for hybrid field-programmable gate array (FPGA) application-specific integrated circuit (ASIC) code acceleration are described. In one example, the computing device includes a FPGA comprising: algorithm circuitry to: perform one or more algorithm tasks of an algorithm, wherein the algorithm to perform a service request that is offloaded to the FPGA; and determine a primitive task associated with an algorithm task of the one or more algorithm tasks; primitive offload circuitry to encapsulate the primitive task in a buffer of the FPGA, wherein the buffer is accessible by an ASIC of the computing device; and result circuitry to return one or more results of the service request responsive to performance of the primitive task by the ASIC.

Technologies for hybrid field-programmable gate array application-specific integrated circuit code acceleration

Technologies for hybrid acceleration of code include a computing device () having a processor (), a field-programmable gate array (FPGA) (), and an application-specific integrated circuit (ASIC) (). The computing device () offloads a service request, such as a cryptographic request or a packet processing request, to the FPGA (). The FPGA () performs one or more algorithmic tasks of an algorithm to perform the service request. The FPGA () determines one or more primitive tasks associated with an algorithm task and encapsulates each primitive task in a buffer that is accessible by the ASIC (). The ASIC () performs the primitive tasks in response to encapsulation in the buffer, and the FPGA () returns results of the algorithm. The primitive operations may include cryptographic primitives such as modular exponentiation, modular multiplicative inverse, and modular multiplication. The results may be returned to the processor () or a network interface controller of the computing device ().

A method includes a unified extensible firmware interface of a compute node identifying an option ROM or an OS boot loader within the compute node, wherein the option ROM or OS boot loader stores a signed image that can be verified using a required digital certificate. The method further includes determining that the unified extensible firmware interface does not store the required digital certificate in a revocation database or in an authorization database. Still further, the method includes automatically identifying the required digital certificate in a database of digital certificates other than the revocation database or the authorization database, and providing the required digital certificate to the authorization database.

Automatic discovery and installation of secure boot certificates

Growing community of inventors

Shanghai, China

Songwu Shen