Western Digital Technologies, Inc.

Songtao Lu

Chih-Chin Liao

Ye Bai

Chien Te Chen

Cheng-Hsiung Yang

Yu Ying Tan

JinXiang Huang

Chia-Hsuan Huang

T Sharanya Kaminda

Ching Chuan Hsieh

Huang Pao Yi

Yuequan Shi

Lin Hui Chen

Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

Printed circuit board for galvanic effect reduction

Devices and methods are described for reducing etching due to galvanic effect within a printed circuit board that may be used, for example, in a data storage device, such as a card-type data storage device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trance, and that is configured to couple the data storage device to a host device. The contact trace is electrically isolated from the rest of the circuitry during a fabrication process. The contact finger and an exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to an impedance trace though at least one of a component and a bond wire.

Printed circuit board trace for galvanic effect reduction

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Shanghai, China

Songtao Lu