Intel Corporation

Songmin Kim

Chee How Lim

Gregory F Taylor

Usman Mughal

Keng L Wong

Timothy M Wilson

Razi Uddin

Robert J Greiner

Greg F Taylor

Michael C Rifani

Navindra Navaratnam

Chi-Yeu Chao

Raghu P Raman

Ying Cole

Maynard C Falconer

Hung-Piao Ma

Michael T Zhang

Chaodan Deng

Steve A Peterson

According to embodiments of the subject matter disclosed in this application, a wide input common mode sense amplifier may include a level shifter stage and an amplifier stage. The level shifter comprises a CMOS differential amplifier that has a rail-to-rail input common mode range. The level shifter accepts two input signals with a common mode voltage in a rail-to-rail range and produces two output signals with a stable common mode voltage. The differential amplifier amplifies the two output signals from the level shifter stage with high gain. The disclosed sense amplifier may be used to measure delay between two discrete time events.

Wide input common mode sense amplifier

A method and apparatus for an integrated circuit having a offset reference circuit block to receive an external voltage reference and output an offset reference voltage are described herein.

On-die offset reference circuit block

A method and a system for configurably generating enabling pulse clocks are disclosed herein. In various embodiments, enabling pulse clocks are configurably generated for a selected one of a first and a second signaling mode, employing a configurable enabling pulse clock generator configurable to so generate the enabling pulse clocks.

Method for configurably enabling pulse clock generation for multiple signaling modes

A method transfers a signal from a transmitting device to a receiving device. The signal is output from the transmitting device using a driving circuit. A reference clock signal is received in the transmitting device. An output clock signal is generated according to the received reference clock signal and a feedback clock signal in a phase locked loop. A delay is provided in a path of the reference clock signal and a path of the feedback clock signal. The delay is configured to make the output signal meet a predetermined valid data timing requirement.

Global I/O timing adjustment using calibrated delay elements

A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.

Closed-loop independent DLL-controlled rise/fall time control circuit

Enabling pulse clocks are configurably generated for a selected one of a first and a second signaling mode, employing a configurable enabling pulse clock generator configurable to so generate the enabling pulse clocks.

Configurable enabling pulse clock generation for multiple signaling modes

Input/output (I/O) clock phase adjustment circuitry for use with I/O buffer circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an I/O clock coupled to be received by an I/O buffer circuit of an integrated circuit chip for I/O data transfers in a system. The phase adjustment circuit includes a phase locked loop (PLL) circuit coupled to receive the system clock through a first delay circuit. The I/O clock generated by the PLL circuit is received through a second delay circuit at a feedback clock input of the PLL circuit. The first and second delay circuits are used to control the phase of the I/O clock generated by the PLL circuit relative to the system clock. In one embodiment, a third delay circuit is included in an I/O data path of the I/O buffer circuit of the integrated circuit. The third delay circuit enables input and output data transmissions from the integrated circuit to be clocked, in effect, out of phase with the I/O clock generated by phase adjustment circuit.

Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock

A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated from a master circuit, and then the reference impedance code is shifted to generate a slave impedance code. The slave impedance code is provided to one or more slave circuits to activate devices in the slave circuit(s). Impedance-generation devices coupled to the slave circuit are then activated one at a time until their generated impedance corresponds to the impedance generated by the slave circuit. The reference impedance code can be incremented or decremented (e.g., shifted) to generate slave impedance codes corresponding to different impedance values, according to impedance requirements of various different circuits that require compensation.

Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation

A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated from a master circuit, and then the reference impedance code is provided (as a slave impedance code) to one or more slave circuits to activate devices in the slave circuit(s). Impedance-generation devices coupled to the slave circuit are then activated one at a time until their generated impedance corresponds to the impedance generated by the slave circuit. The reference impedance code can be incremented or decremented (e.g., shifted) to generate slave impedance codes corresponding to different impedance values, according to impedance requirements of various different circuits that require compensation. Using the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs.

A pull-up circuit has substantially linear current-voltage (I-V) characteristics for use in a bus system, such as in an open drain bus architecture type system. Operation in the linear region of the I-V characteristics is useful in high frequency input/output circuits. The pull-up circuit includes a transistor and a single termination resistor coupled to the transistor, and is simpler than other types of pull-up circuits. This simplicity in design saves area on a chip. The termination resistor in the pull-up circuit can be an n-well resistor formed on the same chip as the transistor, thereby further contributing to the savings in chip area.

Apparatus and method for linear on-die termination in an open drain bus architecture system

In a system, such as an open-drain bus architecture system, a termination impedance can be dynamically coupled or de-coupled from a bus. The termination impedance is coupled to the bus by a dynamic control circuit if a signal is being received from the bus or if a binary 1 is driven on the bus. The termination impedance is de-coupled from the bus by the dynamic control circuit if a binary 0 is driven on the bus. Coupling the termination impedance to the bus improves signal quality by providing a matching impedance. De-coupling the termination impedance reduces power dissipation and improves receiver noise margin.

Apparatus and method for dynamic on-die termination in an open-drain bus architecture system

A dual mode clock input buffer is disclosed. The input buffer includes a first portion for handling a single ended high voltage clock signal and a second portion for handling a differential low voltage clock signal.

Self-configurable clock input buffer compatible with high-voltage single-ended and low-voltage differential clock signals

A method for use with a computer system includes modulating a first clock signal according to a first frequency-time profile to generate a second spread spectrum clock signal. The first clock signal is modulated according to a second frequency-time profile that is asynchronous to the first frequency-time profile to generate a third spread spectrum clock signal.

Asynchronous spread spectrum clocking

A bus termination voltage supply. The invented voltage supply provides an output voltage from an input voltage using biasing and isolation circuits. A voltage isolation circuit couples an input voltage node to an output node to provide the output voltage. The isolation circuit includes a transistor driver element which is coupled to the input voltage node and the output node. The voltage supply also includes a biasing circuit having a voltage divider and a bias transistor. The voltage divider has a first voltage divider element coupling the output node to a voltage divider node. The voltage divider has a second voltage divider element coupling the voltage divider node to a second voltage supply node. The bias transistor couples a control input of the transistor driver element to the second voltage supply node under the control of a bias transistor control input coupled to the voltage divider node. The voltage supply may further include a feedback circuit comprising bias resistor which couples the input voltage supply to the driver control input. This voltage supply may be used to provide a termination voltage for a signal line in a computer system.

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Beaverton, OR, United States of America

Songmin Kim