Globalfoundries Inc.

Songkram Srivathanakul

Huang Liu

Huy Cao

Hung-Wei Liu

Tae Hoon Lee

Garo Jacques Derderian

Rohit Pal

Tsung-Liang Chen

Hsin-Neng Tai

Huey-Ming Wang

Danni Chen

Boaz Alperson

Ruilong Xie

Xiuyu Cai

Haiting Wang

Guillaume Bouche

Jinping Liu

Zhiguo Sun

Moosung M Chae

Ki Young Lee

Sandeep Gaan

Hoong Shing Wong

Ashish Kumar Jha

Chang Ho Maeng

Tae-Hoon Kim

In Soo Jung

A method of forming a self-forming barrier includes selectively removing a portion of a semiconductor dielectric layer to form a three-dimensional pattern within a remaining portion of the dielectric layer. A metal liner layer is disposed on a surface of the pattern to provide a metal lined pattern. A metal filling is disposed over the metal lined pattern, the metal filling being at least partially composed of a metal used in the metal liner layer. Diffusion ions are disposed in one of the metal filling and the metal liner layer. Heat is applied to the metal filling and metal liner layer to diffuse the diffusion ions from one of the metal filling and the metal liner layer into the dielectric layer to form a barrier layer between the metal liner layer and the dielectric layer.

Methods of self-forming barrier formation in metal interconnection applications

One method disclosed herein includes, among other things, forming a process layer on a substrate, forming a carbon-containing silicon dioxide layer above the process layer and forming a patterned mask layer above the carbon-containing silicon dioxide layer. The patterned mask layer exposes portions of the carbon-containing silicon dioxide layer. A material modification process is performed on the exposed portions of the carbon-containing silicon dioxide layer to generate modified portions, and the modified portions are removed. The process layer is etched using remaining portions of the carbon-containing silicon dioxide layer as an etch mask.

Methods for forming mask layers using a flowable carbon-containing silicon dioxide material

Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Gate height uniformity in semiconductor devices

A method of forming a diffusion barrier film over fins and the resulting device are provided. Embodiments include forming silicon fins over a substrate; depositing a borosilicate glass (BSG) liner cap over a first set of the silicon fins; depositing a phosphosilicate (PSG) liner cap over a second set of the silicon fins; and depositing a silicon oxycarbide (SiOC) diffusion barrier film over the BSG and PSG liner caps.

Semiconductor device with diffusion barrier film and method of manufacturing the same

Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate.

Formation of carbon-rich contact liner material

FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions.

FinFET semiconductor devices with local isolation features and methods for fabricating the same

Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material including a carbon-containing species and an elemental carbon disposed therein, the carbon-containing species and the elemental carbon together defining a set carbon content within the carbon-rich contact liner material; and depositing the carbon-rich contact liner material conformally within the at least one contact opening disposed over the semiconductor substrate.

A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

Methods for fabricating integrated circuits utilizing silicon nitride layers

In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Reducing gate height variance during semiconductor device formation

Methods of forming a semiconductor device are provided. The methods include, for example, forming a low-k dielectric having a continuous planar surface, and, after forming the low-k dielectric, subjecting the continuous planar surface of the low-k dielectric to an ethylene plasma enhanced chemical vapor deposition (PECVD) treatment.

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Waterford, NY, United States of America

Songkram Srivathanakul