Shanghai Biren Technology Co., Ltd

Song Zhao

Zhou Hong

ChengPing Luo

GuoFang Jiao

HaiChuan Wang

XiangLiang Yu

Haichuan Wang

Qin Zheng

The invention relates to an apparatus for second offloads in a graphics processing unit (GPU). The apparatus includes an engine; and a compute unit (CU). The CU is arranged operably to: fetch execution codes; when each execution code is suitable to be executed by the CU, execute the execution code; and when each execution code is not suitable to be executed by the CU, generate a corresponding entry, and send a request with the corresponding entry to the engine for instructing the engine to allow a component inside or outside of the GPU to complete an operation in accordance with the corresponding entry.

Apparatus and method for secondary offloads in graphics processing unit

The invention relates to an apparatus for virtualized registers. The apparatus includes register space, group selectors, and a block selector. The register space is divided into physical blocks, each of which includes register groups, and each register group contains registers. Each group selector is coupled to a portion of the register groups in a corresponding physical block, and is arranged operably to enable one of the portion of the register groups in the corresponding physical block in accordance with a first control signal corresponding to a virtual device, or a function performed by the virtual device. The block selector, coupled to the group selectors, is arranged operably to enable one of the group selectors in accordance with a second control signal corresponding to a virtual machine instruction. The virtual machine instruction is translated into an operation of the virtual device.

Apparatus for virtualized registers and method and computer program product for accessing to the same

An artificial intelligence chip and a data operation method are provided. The artificial intelligence chip receives a command carrying first data and address information and includes a chip memory, a computing processor, a base address register, and an extended address processor. The base address register is configured to access an extended address space in the chip memory. The extended address processor receives the command. The extended address processor determines an operation mode of the first data according to the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data.

Artificial intelligence chip and data operation method

The invention relates to a method for compiling code adapted for secondary offloads in a graphics processing unit (GPU). The method, performed by a processing unit, includes: reconstructing execution codes in a first kernel into a second kernel. The second kernel includes an operation table including entries, and computation codes. The computation codes include a portion of the execution codes, and synchronization hooks, and each synchronization hook includes information indicating one entry of the operation table. An order of the portion of the execution codes and the synchronization hooks in the computation codes matches an order of the execution codes in the first kernel, thereby enabling a compute unit (CU) in the GPU to execute the computation codes, and an engine in the GPU to instruct a component inside or outside of the GPU to complete a designated operation in accordance with content of each entry in the operation table.

Apparatus and method and computer program product for compiling code adapted for secondary offloads in graphics processing unit

The invention relates to an apparatus for second offloads in a graphics processing unit (GPU). The apparatus includes an engine; and a compute unit (CU). The engine is arranged operably to store an operation table including entries. The CU is arranged operably to fetch computation codes including execution codes, and synchronization requests; execute each execution code; and send requests to the engine in accordance with the synchronization requests for instructing the engine to allow components inside or outside of the GPU to complete operations in accordance with the entries of the operation table.

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Shanghai, China

Song Zhao