Texas Instruments Corporation

Song Zhao

Mahalingam Nandakumar

Amitava Chatterjee

Zhiqiang (Jeff) Wu

Amitabh Jain

Manoj Mehrotra

Shaofeng Yu

Greg Charles Baldwin

Kamel Benaissa

Jeffrey E Brighton

Shaoping Tang

Samuel Zafar Nawaz

Sarah Liu

Theodore Warren Houston

Haowen Bu

Jiong-Ping Lu

David Barry Scott

Shashank Sureshchandra Ekbote

Kaiping Liu

Youn Sung Choi

Gregory Charles Baldwin

Puneet Kohli

Duofeng Yue

Lance Stanford Robertson

Sue E Crank

Donald S Miles

Youngmin Kim

Lahir Shaik Adam

Nandakumar Mahalingam

Kanan Garg

Mahalingam Nadakumar

A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.

Low temperature coefficient resistor in CMOS flow

An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.

MOSFET with source side only stress

A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.

Integrated circuit having silicide block resistor

Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cmare achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

CMOS fabrication process

A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si&#x2014;H/N&#x2014;H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not through NMOS source and drain anneal. A SiN dielectric layer is deposited such that an area ratio of a Si&#x2014;H peak to a N&#x2014;H peak in a FTIR spectrum is greater than 7 and a tensile stress of the SiN dielectric is greater than 150 MPa. The CMOS integrated circuit is annealed after deposition of the SiN dielectric layer and the SiN dielectric layer is removed from at least a part of the integrated circuit.

Stress memorization dielectric optimized for NMOS and PMOS

Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and drain extension region dopant profiles without significantly inducing gate edge diode leakage. The technique follows the discovery that carbon, which may be used as a diffusion suppressant for dopants such as boron, may produce a gate edge diode leakage if present in significant quantities in the source and drain extension regions. As an alternative to placing carbon in the source and drain extension regions, carbon may be placed in the source and drain regions, and the thermal anneal used to activate the dopant may be relied upon to diffuse a small concentration of the carbon into the source and drain extension regions, thereby suppressing dopant diffusion in these regions without significantly inducing gate edge diode leakage. The increased concentration of carbon in the source and drain regions may permit heavier doping of the source/drain region, leading to improved gate capacitance.

Semiconductor doping with reduced gate edge diode leakage

The present invention provides a method () of designing a circuit. The method comprises specifying () a design parameter for memory transistors and logic transistors and selecting () a test retention-mode bias voltage for the memory transistors. The method further comprises determining () a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining () a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used () to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting () the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

Design method and system for optimum performance in integrated circuits that use power management

The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (). Subsequently, source/drain regions are formed in active regions of an NMOS region (). Then, a capped poly layer is formed over the device (). A second thermal process is performed () that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer

A method for forming metal silicide regions in source and drain regions () is described. Prior to the thermal annealing of the source and drain regions (), germanium is implanted into a semiconductor substrate adjacent to sidewall structures () formed adjacent gate structures (). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (). Following thermal annealing of the source and drain regions (), the implanted germanium prevents the formation of metal silicide spikes.

Silicide method for CMOS integrated circuits

The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted n-type dopants counteract portions of strongly p-type HALO or pocket regions creating a smoother dopant profile or transition from a portion of the active regions to the channel. However, the blanket implant is performed at a relatively low energy so as to not significantly alter one or more other portions of the active regions to other portions of the device.

Process to reduce gate edge drain leakage in semiconductor devices

Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness

Channel implant for improving NMOS ESD robustness

Growing community of inventors

Plano, TX, United States of America

Song Zhao