Texas Instruments Corporation

Song Wu

Sridhar Ramaswamy

Bhavesh G Bhakta

Yaqi Cheng

Dennis G Mannering

Robert Floyd Payne

Michael Oliver Polley

Donald Phillip Shaver

Domingo G Garcia

Xiaolin Lu

Alan Gatherer

Gene A Frantz

Nirmal Chindhu Warke

Hassan Omar Ali

Mohammed Nafie

Kofi Dankwa Anim-Appiah

Walter Y Chen

Douglas B Weiner

Yaser M Ibrahim

William C Timm

Terence J Riley

Paul E Schurr

An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signals from the sampler and generates equalization signals therefrom. The summer couples to the sampler and the filter and combines together the input communication signal with the equalization signals. Further, a plurality of clocks control timing associated with the sampler. These clocks have frequencies that are less than the predetermined data rate of the digital decision output signals.

High speed decision feedback equalizer

In one aspect, the present invention provides a system and method for selecting precursor equalizer coefficients and a serializer deserializer (SERDES) incorporating the system or the method. In one embodiment, the system includes: (1) a cost definer configured to generate an eye height cost function based on continuous-time channel and crosstalk symbol responses pertaining to a particular serial link and (2) a cost evaluator associated with the cost definer and configured to evaluate the eye height cost function based on a particular criterion thereby to produce coefficients for a precursor equalizer to be applied with respect to the particular serial link.

System and method for selecting precursor equalizer coefficients and serializer deserializer incorporating the same

A filter includes a tap multiplication circuit and a tap digital-to-analog ('DAC') unit coupled to the tap multiplication circuit. Further, a plurality of clocks are provided that control timing associated with the tap multiplication circuit and that permit one tap multiplication to be output while another tap multiplication is being computed for a 1/N rate implementation.

High performance FIR filter

A method, and associated storage medium containing software and a system, includes extracting a time domain impulse response from parameters that characterize a communication channel, generating a probability distribution function (PDF) of an output voltage based on the impulse response; and computing a relationship between bit error rate and voltage margin based on the final probability distribution function. Generating the PDF of the output voltage may comprise one or more of the following acts: quantizing the impulse response into a plurality of quantized levels, assigning taps to the quantized levels and determining a number of taps assigned to each quantized level, determining allowable voltage levels for each quantized level, and determining a probability of occurrence of each allowable voltage level, determining a PDF for each voltage level; and convolving all of the PDFs for the various voltage levels to obtain the PDF of the output voltage.

Methodology for designing high speed receivers below a target bit-error-rate

Disclosed are integrated circuits having multiple electromagnetically emissive devices, such as LC oscillators. The devices are formed on an integrated circuit substrate and are given different planar orientations from each other. Particular integrated circuit packages disclosed are 'flip-chip' packages, in which solder bumps are provided on the integrated circuit substrate for flipping and mounting of the finished integrated circuit upon a printed circuit board or other substrate. The solder bumps provide conductive connections between the integrated circuit and the substrate. The orientations and positioning of the emissive devices are such that one or more of the solder bumps are interposed between neighboring emissive devices to act as an electromagnetic shield between them.

Reducing the coupling between LC-oscillator-based phase-locked loops in flip-chip ASICs

A multi-client ADSL modem network () that can be configured for a home or office network when multiple ADSL client modems () are installed in different communication terminals (). One ADSL modem () at a central office () coordinates the remote multi-client modems () for communication over a single twisted pair loop carrier phone line (), allowing the connected modems () to communicate not only with the CO modem (), but also with each other by sharing frames, tones, or by code division techniques on upstream channels. The CO modem () operates as a network hub and/or arbitrator, and facilitates one ADSL modem to become the master modem and maintain a superframe. The present invention provides home network ADSL service without extra wiring or equipment, thus providing a low cost approach for home networking of ADSL service.

Multi-client ADSL modem

The present invention provides a method and system of transceiving a data signal in a HomePNA type network. The transceiver enables digital signal processing of the data signal compliant with the HomePNA 10M8 specification in an Open System Interconnection type network over a shared medium such as a client's home phoneline (). The transceiver can be implemented in each station () of the HomePNA single-segment network () in which each station is logically connected to the same shared channel on the phonewire (). The transceiver enables transmission of the data signal in burst on the shared channel while complying with the spectral mask (), temporal mask () and other electrical requirements as specified in the HomePNA 10M8 technology.

HomePNA 10M8 compliant transceiver

A DMT device having an analog front end for receiving an analog signal, a converter for converting the analog signal to a digital signal, a FFT for converting the digital signal from the time domain to the frequency domain and feeding the digital signal to a frequency domain equalizer having variable coefficients for flattening the converted digital signal. The frequency domain equalizer includes a gain corrector coupled to the FFT to compensate the channel frequency rolloff and make each tone approximately the same amplitude before phase rotation and a phase rotator portion responsive to the output of the gain corrector to track small channel variation. Also included is circuitry for updating the coefficients of the frequency domain equalizer, preferably in the form of a slicer for controlling the frequency domain equalizer by feeding back an error signal thereto. The error signal is preferably fed back to the phase rotator portion of the frequency domain equalizer.

MDSL DMT architecture

A method ( ) of communicating bit groups between a first DSL modem (M ) and a second DSL modem (M ). The method receives ( ) at the first DSL modem a plurality of bit groups (FF -FF ) from the second DSL modem. Each of the plurality of bit groups comprises a plurality of bit sub-groups (W -W ), and each of the plurality of bit sub-groups has an order of location. For each of the plurality of bit groups, the method determines ( ) whether bits of at least one sub-group having a common order of location comprise at least one erroneous bit. In response to this determination, the method stores ( ) in the first DSL modem a record (InMaskBuff) of whether the at least one sub-group having the common order of location comprises at least one erroneous bit. From this record, various other steps ( ) may be taken in the preferred embodiment, including suppressing ( ) the at least one sub-group from communicating valid information from the second DSL modem to the first DSL modem.

Circuits, systems, and methods for error elimination in a digital subscriber line modem

A method of modem communications between first and second modems ( ) over a communications facility (TWP). The method operates the first modem ( ) to issue communications to the second modem ( ) over the communications facility. These communications comprise a plurality of subchannel signals (n). The method also operates the second modem to perform various steps. In one of these steps, the second modem converts ( ) the communications from time domain communications to frequency domain communications, where the frequency domain communications signals comprise a plurality of subchannel signals. Each of these plurality of subchannel signals comprises an amplitude portion and a phase portion. In another of these steps, the second modem equalizes ( ) the amplitude portion of each of the plurality of subchannel signals using fixed gain factors (GE(n))corresponding to each of the plurality of subchannel signals. In still another of these steps, the second modem equalizes ( ) the phase portion of each of the plurality of subchannel signals using adjustable phase factors (PE(n)) corresponding to each of the plurality of subchannel signals. The adjustable phase factors are adjusted in response to previous communications from the first modem to the second modem.

Adaptive frequency domain equalizer circuits, systems, and methods for discrete multitone based digital subscriber line modem

A modem ( ) including receive circuitry ( ) implemented by way of a digital signal processor ( ) is disclosed. The receive circuitry ( ) operates according to a receive clock (CLK ) that is based upon the output of a free run oscillator ( ). An incoming frequency multiplexed signal (f(t)) is sampled by an analog-to-digital converter ( ) and demodulated by way of a Fast Fourier Transform function ( ). After such demodulation, a phase rotation function ( ) applies a phase shift to the demodulated signal corresponding to an estimated phase offset (&tgr;) between the receive clock (CLK ) and a pilot signal (P) transmitted by the transmitting modem; a finite impulse response filter function ( ) applies a digital filter to the demodulated signal to correct for phase error based upon an estimated frequency offset (&Dgr;). According to another disclosed embodiment, a pre-emphasis FIR filter function ( ) and a pre-emphasis phase rotation function ( ) are applied to an upstream singal, based upon the estimated phase offset (&eegr;) and frequency offset (&Dgr;).

Phase and frequency offset compensation in a telecommunications receiver

An equalization technique for an ADSL data communications system is disclosed. The effective channel overall response is made a window of length I equal to the length of the cyclic prefix. The response energy output of filtering is monitored against a preset threshold value to adaptively position the window.

Time domain equalizer for ADSL

A method of initializing the operation of a remote modem (,) and central office modem (,) for asymmetric subscriber line modem communications over a twisted pair wire facility (TWP), using discrete multi-tone technology, is disclosed. The initialization process begins with the remote modem (,) issuing an initialization request, in response to which the central office modem (,) issues an acknowledgment. The remote modem (,) includes a low-cost analog filter (,) for separating upstream communication echoes from downstream data. This analog filter (,) increases the duration of impulse response over the channel, and thus requires time-domain equalization (TEQ) process (,) performed by the remote modem (,) to filter relatively long circular prefixes, so that intersymbol interference is eliminated. Transceiver training processes (,R,,C) are carried out, through the generation of a pseudo-random sequence of frames by the central office modem (,), the receipt of which is used by the remote modem (,) to establish its TEQ coefficients and taps in an optimal manner.

Digital subscriber line modem initialization

A method to estimate the bit loading on each tone of a DMT digital subscriber loop system is disclosed. A generic bit-mapping table is given for different sizes of constellations to save memory space.

Bit loading and rate adaptation on DMT DSL data transmission

A clipping protection scheme for a discrete multi-tone (DMT) digital subscriber loop modem telecommunications system determines the occurrence of clipping by checking the overflow bits in the IFFT status register. The transmitter then sends a predefined data stream to notify the receiver of the event, and then breaks the data into two frames for consecutive transmission to the receiver.

Growing community of inventors

Plano, TX, United States of America

Song Wu