Sun Microsystems, Inc.

International Business Machines Corporation

Oracle International Corporation

Oracle America, Inc.

Song C Kim

Kuan-yu J Lin

Heechoul Park

Rajinder Paul Singh

Hao Chen

Peichun Peter Liu

Hoyeol Cho

Jungyong Lee

Pei-Chun Peter Liu

Lancelot Y Kwong

James M Kaku

Kuan-Yu J Lin

Ken Shin

Dynamic power consumption is reduced by clock gating registers that synchronize memory input signals in an embedded memory array. Where a memory enable signal associated with a memory interface input signal does not meet setup timing for clock gating input registers of the memory interface signal, a clock gate enable signal may be generated prior to evaluation of the memory enable signal. The clock gate enable signal includes all functions of the memory enable signal and additional conditions because it is generated prior to evaluation of conditions on which the memory enable signal may depend. Pre-evaluated clock gate enable signals may be generated within a processor core and used to clock gate read address registers, write address registers, data input registers, and/or CAM reference address registers of an embedded memory array.

Memory array clock gating scheme

Methods and apparatuses are presented for improving reduced power operations in embedded memory arrays. Some embodiments may include a microprocessor, the microprocessor including at least one execution unit, a memory coupled to the execution unit, the memory including, a memory cell comprising a memory cell bus, a power circuit selectively coupling the memory cell bus to a first power plane and a second power plane, where the memory cell bus is coupled to the second power plane when the power circuit is substantially off, and a bit line pre-charge circuit coupled to the power circuit, where the power circuit selectively couples the first power plane to the pre-charge circuit for a predetermined period of time.

Methods and apparatuses for improving reduced power operations in embedded memory arrays

A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage level switch, a recycle charge storage, a precharge switch, a write enable switch, and column decoder. The cell voltage level switch is connected to a low power supply and a high power supply and has two states of operation: a write operation state and a read operation state. For each state of operation, the voltage level switch selectively provides a power supply if a column has been selected or if the operation is a read or write. The recycle charge storage stores excess charge from SRAM cells after a read operation or after a write operation in unselected columns. After the read or write operation, the recycle charge storage discharges excess charge to the bitlines during bitline precharging.

Write and read assist circuit for SRAM with power recycling

A dynamic set/reset circuit is provided with a first feedback line and a second feedback line. The first feedback line provides an interlocked feedback signal which permits high frequency operation of the set/reset circuit. The second feedback line prevents the interlocked feedback signal from causing the circuit to improperly change state until the next cycle of the circuit. In this manner, the circuit will operate properly despite an unexpectedly wide pulse on an input line. The dual feedback can be used on the set or reset inputs of a set/reset circuit, or both, and the set/reset circuit can be used in various logic and high speed applications, such as within a microprocessor.

Dynamic set/reset circuit with dual feedback

The present invention is directed to an apparatus for precharging complementary data circuits. The apparatus comprises two hold circuits, one for storing the data and the other for storing its complement. A signal for initiates precharging the hold circuits to the same signal level, where the signal for initiating the precharging of the hold circuits is dependent on the hold circuits' outputs.

Dynamic circuit for capturing data with wide reset tolerance

An apparatus and method for resetting a dynamic logic circuit is disclosed. The apparatus includes an input circuit coupled to a plurality of input nodes wherein the input circuit comprises a plurality of FETs connected between a first voltage node and a dynamic node of a logic circuit. The gate electrode of each input circuit FET is connected to one of the input nodes. Precharged FET is connected between the dynamic node and a second voltage node. The precharge FET is configured to conduct a current for precharging the dynamic node to a predetermined voltage. An inverter is coupled between the dynamic node and an output node. A precharge control circuit is connected in a feedback path between the output node and the precharge FET. The precharge control signal activates the precharge control FET in response to a RESET pulse width and deactivates the precharge FET in response to the voltage on the dynamic node. As such, the precharge FET is controlled and the dynamic node is properly precharged independent of the RESET pulse width.

Method of charging a dynamic node

Apparatus and method for resetting a dynamic logic circuit

A dynamic pulse register which uses a standard clock signal and exhibits reduced propagation delay. The dynamic pulse register includes a precharge logic block configured to precharge an evaluate signal and an evaluate complement signal during a precharge phase. During an evaluate phase, a pulldown logic block is configured to discharge either the evaluate or evaluate complement signal in response to a valid data input to the pulse register. A driver logic block is configured to convey a data out signal as the complement of the evaluate complement signal, and a data out complement signal as the complement of the evaluate signal. Either the data out signal or the data out complement signal is thus charged (thereby producing the rising edge of the output pulse) in response to the discharging performed by the pulldown logic block. A subsequent rising edge of a delayed version of the clock signal is employed by a reset unit to generate a precharge signal which charges the evaluate and evaluate complement signal back to their precharge logic state. The data out and data out complement signals are correspondingly discharged, producing the falling edge of the output pulse and terminating assertion of the precharge signal. The dynamic pulse register is thus able to generate a pulse output in a single logic stage employing a standard clock signal. The speed of the pulse register may be advantageously increased without introducing the complexity of an early clock signal.

Method for generating a pulse output in a dynamic register

Dynamic pulse register with scan functionality

A decode register which receives a first plurality of input lines. If the decode register is not in a scan mode during a given clock cycle, the decode register is configured to convey a decoded output value in response to an input value conveyed on the first plurality of input lines. The decode register also includes a scan decode unit, which receives a second plurality of input lines. When operating in scan mode during a given clock cycle, the decode register is configured to convey a second decoded output value in response to a second input value conveyed on the second plurality of input lines. The second plurality of input lines comprise a scan input line and one or more feedback lines which each correspond to a value on the scan input line during a previous clock cycle. The decode register also includes an encoder which is configured to receive a value indicative of the second decoded output value. In response to receiving the decoded input value, the encoder is configured to convey a corresponding encoded output value on a scan output line and the one or more feedback lines. The encoder implements a serial shift function for the scan input of the decode register. In this manner, a single scan input bit may be used to test each of a plurality of output lines while ensuring only one output line is active at a time. Additionally, with only a single logic stage, the decode register exhibits reduced propagation delay.

Decode register with scan functionality

A memory circuit which steers read/write data to a memory array including a plurality of columns (at least one of which is redundant). Coupled to the bit line of each column are a normal mode write transistor and a redundant mode write transistor. If a failing column is detected during manufacturing testing of the memory array, a repair signal for each of the failing column and subsequent columns in the array are de-asserted. When a write operation is performed on the array, an input data bit is provided corresponding to each non-redundant column in the array. The input data bit written to a particular bit line, however, depends upon the state of the repair signal for that column. If the repair signal for a particular column is asserted, the input to the normal mode write transistor is conveyed as write data. Conversely, the input to the redundant mode write transistor is conveyed as write data if the repair signal is de-asserted for a particular column. Similar circuitry is also included to perform steering during a read operation. By proper assertion of the repair signal for each column, the memory circuit causes failing columns to be bypassed during operation of the memory array. The configuration of this memory circuit may advantageously increase the speed of the array for read/write operations. In addition, the loading on each bit line may be decreased, which advantageously decreases write recovery time for the array.

Memory column redundancy circuit

A compare circuit for a content-addressable memory within a computer system is disclosed. In accordance with a preferred embodiment of the present invention, a compare circuit for a content-addressable memory comprises a pair of storage node lines, a pair of compare lines, and two sets of transistors. The pair of storage node lines are complementary to each other and are connected to a memory cell of the content-addressable memory for determining a state of the memory cell. In a like manner, the pair of compare lines are also complementary to each other. The first set of transistors are four transistors connected in series to be enabled by a logical one from one of the storage node lines for allowing a signal from one of the compare lines to propagate to an output. The second set of transistors are also four transistors connected in series to be enabled by a logical zero from the same storage node line for allowing a signal from the other compare line to propagate to the output. Under the present invention, a signal from either compare line needs to propagate through only one level of transistors in order to reach the output.

Compare circuit for content-addressable memories

Logic circuitry utilizing the advantages of static and dynamic design techniques utilize feed-forward from the inputs to the logic circuit and feed-back from the output of the logic circuit in order to provide a RESET signal to precharge the logic circuit to a predetermined state. This technique also provides for initialization of the circuit before the arrival of data input signals.

Growing community of inventors

Santa Clara, CA, United States of America

Song C Kim