Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Sonam Agarwal

Vijay Chinchole

Pavithra Devaraj

Yan Li

Nisha Padattil Kuliyampattil

Akash Agarwal

Naman Rastogi

A memory circuit included in a computer system includes a memory array that stores multiple program instructions included in compressed program code. In response to receiving a fetch instruction from a processor circuit, the memory circuit may retrieve a particular instruction from the memory array. The memory circuit may, in response to a determination that the particular instruction is a particular type of instruction, retrieve additional program instructions from the memory array using an address included in the particular instruction, and send the particular program instruction and the additional program instructions to the processor circuit.

Memory circuit for halting a program counter while fetching an instruction sequence from memory

A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

Dynamic re-evaluation of parameters for non-volatile memory using microcontroller

A method for reducing firmware size and increasing firmware performance. Core timing control conditions used by a die controller are converted into production ready core timing control conditions, from which firmware instructions are then generated. The production ready core timing control conditions comprise a plurality of fixed core timing control conditions. The firmware instructions are modified to determine core timing control condition values for fixed core timing control conditions before implementing storage operations, to store the core timing control condition values in global condition registers, and to modify references to fixed core timing control conditions to access the values in those global condition registers. Finally, the modified firmware instructions are stored on the die controller, which comprises a microcontroller configured to execute them.

Reducing firmware size and increasing firmware performance

Growing community of inventors

Jaipur Rajasthan, India

Sonam Agarwal