Qualcomm Incorporated

Sonali Jabreva

Santhosh Reddy Akavaram

Prakhar Srivastava

Yogananda Rao Chillariga

Sridhar Anumala

Madhu Yashwanth Boenapalli

Surendra Paravada

Ramacharan Sundararaman

Ravindranath Doddi

Manish Garg

Chintalapati Bharath Sai Varma

Rajendra Varma Pusapati

Khushboo Kumari

Sanjay Verdu

Aspects relate to interrupting memory access during background operations of a memory device. In one example, a host for a memory device includes background operation circuitry configured to permit a background operation by a memory device. The host is coupled to the memory device through a bus. The host receives an operation completed notification from the memory device to indicate that the memory device has completed performing the background operation. Memory access command circuitry is configured to receive a memory access command. The memory access command concerns reading or writing data to the memory device coupled to the host. The memory access command circuitry initiates a wait at the host for the memory access command, and sends the memory access command to the memory device in response to receiving the operation completed notification.

Interrupting memory access during background operations on a memory device

Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link configuration by a computing device. Embodiments may include selecting, by a PCIe device, a predetermined PCIe link speed based on a PCIe link configuration mode of a PCIe system of a plurality of PCIe link configuration modes of the PCIe system, and selecting, by the PCIe device, a PCIe link width of one lane for configuring the PCIe link. Embodiments may include selecting a PCIe link speed level lower than a current PCIe link speed in response to a reliability indicator exceeding a reliability threshold for a first PCIe link configuration mode. Embodiments may include selecting a maximum PCIe link speed for the PCIe link for a second PCIe link configuration mode. Embodiments may include increasing the PCIe link width in response to a requested bandwidth exceeding a configuration bandwidth of the PCIe link.

Mechanism to enhance PCIe generation switching

Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the write throughout of a data storage device. In some aspects, the storage device can be provided with multiple write buffers to improve write throughput. In some aspects, the data storage device can continue to handle commands using a command queue while performing a write buffer flush operation. Therefore, the data storage device can avoid suspending the write buffer flush operation when a new command is received by the command queue. In some aspects, the storage device can perform a write buffer flush operation when a command queue is not empty.

Memory devices write buffer management

Methods and apparatuses are provided to reduce latencies associated with state transitions in die-to-die interconnect architectures. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to the first event, the physical layer transitions to a lower power state where one or more clock configuration values are read from registers and stored in memory. The physical layer then detects a second event indicating a transition to an active state. In response to the second event, the physical layer reads the clock configuration values from the memory, and writes the clock configuration values to the registers. The physical layer then transitions to a power stabilization state, and remains in the power stabilization state for an amount of time to allow clocks to stabilize. The physical layer then transitions to a training state.

Apparatus and methods for reducing latencies associated with link state transitions within die interconnect architectures

Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the memory resource utilization of a data storage device that uses nonvolatile memory (NVM) to store data. In some aspects, the data storage device can be provided with multiple write buffers to improve the write throughput of the device. In some aspects, the data storage device can use a utilization array to keep track of the utilization information of each write buffer. In some aspects, the data storage device can repurpose the memory of a write buffer with low utilization to serve an active logical unit which becomes full, thus preserving the function of the write buffer of the active logical unit.

Write buffer and logical unit management in a data storage device

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Firozabad, India

Sonali Jabreva