Xilinx, Inc.

Sonal Santan

Hem C Neema

Soren T Soe

Cheng Zhen

Ralph D Wittig

Amit Kumar

Stephen P Rozum

Kumar Deepak

Yenpang Lin

Valeria Mihalache

Fernando J Martinez Vallina

Khang Kim Dao

Kyle Corbett

Sudipto Chakraborty

Henry E Styles

Yu Liu

Lizhi Hou

Min Ma

Jeffrey M Fifield

Philip Bryn James-Roxby

David A Knol

Ravi Nagarajarao Kurlagunda

Sheng Zhou

Umang Parekh

Nik Cimino

Devadas Varma

Nabeel Shirazi

Ashish Sirasao

Sebastian Turullols

Hare Krishna Verma

Raymond Kong

Ashish Gupta

Elliott Delaye

Jindrich Zejda

Jun Liu

Aaron Ng

Salil Ravindra Raje

Chandrasekhar S Thyamagondlu

Jeffrey H Seltzer

Ehsan Ghasemi

David K Liddell

Pradip Jha

Xiao Teng

Brian S Martin

Ravinder Sharma

Yongjun Wu

Julian M Kain

Sumit Roy

Ryan Radjabi

Yi Wang

Sean Settle

Suman Kumar Timmireddy

Kenneth Chan

Yau-Tsun Steven Li

Spenser Don Gilliland

Heera Nand

Yong Li

Ch Vamshi Krishna

Kaustuv Manji

Christopher J Case

Sandeep S Deshpande

Bin Ochotta

Manjunath Chepuri

Sushama Ghanekar

Idris I Tarwala

Susheel Kumar Puthana

Lixin Huang

Pratima Gupta

Yidong Zhang

Chien-Wei Lan

Karen Xie

Pranjal Joshi

Sarabjeet Singh

Fei Rui

Ethan T Parker

Charles Kwok-Wah Lo

Himanshu Choudhary

Bennet An

Charles Kwah-Wah Lo

Ravi N Kurlagunda

Khang K Dao

Kwok-Wah Lo

Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device runtime, as executed by the device processor, invokes a runner program associated with the software kernel. The runner program can map a physical address of the descriptor to a virtual memory address corresponding to the descriptor that is usable by the software kernel. The runner program can execute the software kernel. The software kernel can access data specified by the descriptor using the virtual memory address as provided by the runner program.

Transparent and remote kernel execution in a heterogeneous computing system

Embodiments herein describe techniques for preparing and executing tasks related to a database query in a database accelerator. In one embodiment, the database accelerator is separate from a host CPU. A database management system (DBMS) can offload tasks corresponding to a database query to the database accelerator. The DBMS can request data from the database relevant to the query and then convert that data into one or more data blocks that are suitable for processing by the database accelerator. In one embodiment, the database accelerator contains individual hardware processing units (PUs) that can process data in parallel or concurrently. In order to process the data concurrently, the data block includes individual PU data blocks that are each intended for a respective PU in the database accelerator.

Parallel compute offload to database accelerator

Embodiments herein describe partitioning an acceleration device based on the needs of each user application executing in a host. In one embodiment, a flexible queue provisioning method allows the acceleration device to be dynamically partitioned by pushing the configuration through a control command queue to the device by management software running in a trusted zone. The new configuration is parsed and verified by trusted firmware, which, then, creates isolated IO command queues on the acceleration device. These IO command queues can be directly mapped to a user application, VM, or other PCIe devices. In one embodiment, each IO command queue exposes only the compute resource assigned by the trusted firmware in the acceleration device.

Flexible queue provisioning for partitioned acceleration device

An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of the validation on a per host command basis. The host commands are executable by the processor to manage functions of the integrated circuit. The queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.

Extensible device hosted root of trust architecture for integrated circuits

A unified container file can be selected using computer hardware. The unified container file can include a plurality of files embedded therein used to configure a programmable integrated circuit (IC). The plurality of files can include a first partial configuration bitstream and a second partial configuration bitstream. The unified container file also includes metadata specifying a defined relationship between the first partial configuration bitstream and the second partial configuration bitstream for programming the programmable IC. The defined relationship can be determined using computer hardware by reading the metadata from the unified container file. The programmable IC can be configured, using the computer hardware, based on the defined relationship specified by the metadata using the first partial configuration bitstream and the second partial configuration bitstream.

Unified container for hardware and software binaries

Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator using a library. The neural network application may execute on a host computing system while the neural network accelerator executes on a massively parallel hardware system, e.g., a FPGA. The library operates a pipeline for submitting the tasks received from the neural network application to the neural network accelerator. In one embodiment, the pipeline includes a pre-processing stage, an FPGA execution stage, and a post-processing stage which each correspond to different threads. When receiving a task from the neural network application, the library generates a packet that includes the information required for the different stages in the pipeline to perform the tasks. Because the stages correspond to different threads, the library can process multiple packets in parallel which can increase the utilization of the neural network accelerator on the hardware system.

Machine learning runtime library for neural network acceleration

An example computing system includes: a processing system, a hardware accelerator coupled to the processing system, and a software platform executing on the processing system. The hardware accelerator includes: a programmable integrated circuit (IC) configured with an acceleration circuit having a static region and a programmable region; a memory in the programmable IC configured to store metadata describing interface circuitry in at least one of the static region and the programmable region of the acceleration circuit. The software platform includes program code executable by the processing system to read the metadata from the memory of the hardware accelerator.

Data-driven platform characteristics capture and discovery for hardware accelerators

A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

High throughput circuit architecture for hardware acceleration

Examples herein describe techniques for launching and executing a pipeline formed by heterogeneous processing units. A system on a chip (SoC) can include different hardware elements which form a collection of heterogeneous processing units, such as general purpose processor, programmable logic array, and specialized processors. These processing units are heterogeneous meaning their underlying hardware and techniques for processing data are different, in contrast to a system that using homogeneous processing units. In the embodiments herein, the heterogeneous processing units can be arranged into a pipeline where each stage of the pipeline is performed by one of the processing units.

Heterogeneous execution pipeline across different processor architectures and FPGA fabric

Supporting multiple clients on a single programmable integrated circuit (IC) can include implementing a first image within the programmable IC in response to a first request for processing to be performed by the programmable IC, wherein the request is from a first process executing in a host data processing system coupled to the programmable IC, receiving, using a processor of the host data processing system, a second request for processing to be performed on the programmable IC from a second and different process executing in the host data processing system while the programmable IC still implements the first image, comparing, using the processor, a second image specified by the second request to the first image, and, in response to determining that the second image matches the first image based on the comparing, granting, using the processor, the second request for processing to be performed by the programmable IC.

Supporting access to accelerators on a programmable integrated circuit by multiple host processes

Embodiments herein describe techniques for validating binary files used to configure a hardware card in a computing system. In one embodiment, the hardware card (e.g., an FPGA) includes programmable logic which the binary file can configure to perform a specialized function. In one embodiment, multiple users can configure the hardware card to perform their specialized tasks. For example, the computing system may be server on the cloud that hosts multiple VMs or a shared workstation. Permitting multiple users to directly configure and use the hardware card may present a security risk. To mitigate this risk, the embodiments herein describe techniques for validating encrypted binary files.

Enabling integrity and authenticity of design data

A computer program product can include a non-transitory computer readable storage medium storing a unified container. The unified container can include a header structure, wherein the header structure has a fixed length and specifies a number of section headers included in the unified container. The unified container can include a plurality of section headers equivalent to the number of section headers specified in the header structure. The unified container can include a plurality of data sections corresponding to the plurality of section headers on a one-to-one basis. The plurality of data sections includes a first data section including a hardware binary and a second data section including a software binary. The hardware binary and the software binary are configured to program a programmable integrated circuit. Each section header specifies a type of data stored in the corresponding data section and specifies a mapping for the corresponding data section.

A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the host system and the kernel circuit.

Streaming platform flow and architecture for an integrated circuit

Updating firmware in an programmable integrated circuit (IC) includes determining, using a processor of a computer, a base address register (BAR) of an accelerator card from a device data file, wherein the accelerator card includes a programmable IC and is connected to the computer via a communication bus, mapping, using the processor, a feature PROM and a flash programmer circuit of the programmable IC to local memory of the computer using the BAR, and reading, over the communication bus, the feature PROM on the programmable IC to determine a programming mode for programming an external flash memory coupled to the flash programmer circuit. Based on the programming mode and using the processor, firmware is provided to the flash programmer circuit on the programmable IC via the communication bus. The flash programmer circuit is configured to program the firmware into the external flash memory.

Updating firmware for programmable integrated circuits in computing environments

An integrated circuit (IC) may include a scheduler for hardware acceleration. The scheduler may include a command queue having a plurality of slots and configured to store commands offloaded from a host processor for execution by compute units of the IC. The scheduler may include a status register having bit locations corresponding to the slots of the command queue. The scheduler may also include a controller coupled to the command queue and the status register. The controller may be configured to schedule the compute units of the IC to execute the commands stored in the slots of the command queue and update the bit locations of the status register to indicate which commands from the command queue are finished executing.

Embedded scheduling of hardware resources for hardware acceleration

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San Jose, CA, United States of America

Sonal Santan