Intel Corporation

Son H Lam

Henry W Koertzen

Steven D Patzer

Joseph T Dibene, Ii

James W Alexander

Devadatta V Bodas

Bruce A Clark

Steve J Brown

Steve Rodden

Rick Feightner

Mark Albrecht

Todd Whitaker

Bob Eldridge

Pat Rodden

Carma Caughlan

Suzanne Taylor

Wei-Tong Sun

Greg Lento

Dave Heasty

Kyle Fox

Bun Tan

Larry Altendorf

Mike Midghall

Rob Armstrong

Kai Cheng

Ian M Steiner

Krishna Kant

Howard S David

Edward R Stanford

Patrick Douglas James

Gopikrishna Jandhyala

Jospeh T Dibene, Ii

In accordance with some embodiments, margining routines to determine acceptable voltage command values for specific CPU implementations at one or more different operating levels may be provided.

Supply margining Method and apparatus

Supply margining method and apparatus

Disclosed is a switching voltage regulator circuitry controlled to supply a voltage to at least a portion of an integrated circuit (IC). Information corresponding to a current load for a different power state of at least a portion of the IC is received. The switching voltage regulator circuitry is controlled to adjust the voltage to a different value based at least in part on the received information. Disclosed is a voltage received for a power state of at least a portion of an IC having first logic to perform one or more functions and second logic integrated with the first logic. Information corresponding to a current load for a different power state of at least a portion of the IC is sent from the second logic to voltage regulator control logic to adjust the voltage to a different value.

Supply voltage control based at least in part on power state of integrated circuit

Methods and apparatus relating to optimization of performance and/or power consumption during memory power down state are described. In an embodiment, a memory controller may include logic to cause one or more ranks of a DIMM to enter a clock enable slow mode. Other embodiments are also described.

Optimizing performance and power consumption during memory power down state

Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.

Systems, methods and apparatuses for clock enable (CKE) coordination

For one disclosed embodiment, switching voltage regulator circuitry may be controlled to supply a voltage to at least a portion of an integrated circuit. Information corresponding to a current load for a different power state of at least a portion of the integrated circuit may be received. The switching voltage regulator circuitry may be controlled to adjust the voltage to a different value based at least in part on the received information. For another disclosed embodiment, a voltage may be received for a power state of at least a portion of an integrated circuit having first logic to perform one or more functions and second logic integrated with the first logic. Information corresponding to a current load for a different power state of at least a portion of the integrated circuit may be sent from the second logic to voltage regulator control logic to adjust the voltage to a different value. Other embodiments are also disclosed.

Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.

Systems, methods and apparatuses for rank coordination

Embodiments of the invention supply power to DRAM or other memory devices with a multi-phase voltage regulator. A power controller coupled to the multi-phase voltage regulator causes one or more phases of the multi-phase voltage regulator to be activated or deactivated (shed) according to predetermined criteria. Embodiments of the invention thus improve power management by providing one or more reduced power states for the memory devices. Other embodiments are described.

System and method for memory phase shedding

A multiprocessor computer system implements fault resilient booting by using appliance server management. While previous systems have utilized fault resilient booting, it has required the use of a baseboard management controller chip. The present invention avoids the need for this chip by utilizing the appliance server management architecture. The testing of the processors and the determination of the bootstrap processor is controlled by the system I/O device utilizing a timer and a latch.

Fault resilient booting for multiprocessor system using appliance server management

A technique for reporting a hard disk drive failure in a computer system includes detecting a failure of one of a plurality of hard disk drives and reporting the failure to a CIMOM (Conceptual Information Model Object Manager) which in turn forwards a message by an LRA (Local Response Agent) to a PMP (Platform Management Provider which in turn forwards a command to an SMC (Server Management Controller), which forward the command to an HSC (Hot-Swap Controller) activate a display, the display reporting the failure or of a particular one of the hard disk drives to a user.

Reporting hard disk drive failure

A method and apparatus for protecting a low voltage processor inserted in a high voltage processor connector includes a circuit that determines whether power can be safely asserted to the connector, or whether power should be disabled due to a non-compliant processor. A method enables power to the connector upon a determination that a compliant processor, a termination card, or an empty connector is present.

Preventing damaging of low voltage processor in high voltage system

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Puyallup, WA, United States of America

Son H Lam