International Business Machines Corporation

Son Dao Trong

Silvia Melitta Mueller

Michael Klein

Martin Stanley Schmookler

Klaus Michael Kroener

Juergen Haess

Jochen Preiss

Lawrence Joseph Powell, Jr

Christian Jacobi

Eric M Schwarz

Maarten Jakob Boersma

Rolf Sautter

Hans-Werner Tast

Wilhelm Ernst Haller

Klaus J Getzlaff

Christophe J Layer

Klaus Helwig

Klaus P Gungl

Gunter Gerwig

Markus Loch

Luis Parga Cacheiro

A method for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections. Two leading-one correction terms are generated for the fraction in the multiplier floating-point number and two leading-one correction terms are generated for the fraction in the multiplicand floating-point number. The floating-point numbers may be single-precision or double-precision. Each leading-one correction term for the single-precision case is appended to the left of an intermediate partial product sum in the adder array that is an input to an adder so as to not to extend the bits in the input further to the left than the bits in another input to the adder. Each leading-one correction term for the double-precision case replaces an adder input that is unused when base-2 floating-point numbers are multiplied.

Optimized structure for hexadecimal and binary multiplier array

A method for operating a fused-multiply-add pipeline in a floating-point unit of a processor is disclosed. A multiplication is initially performed between a first operand and a second operand in a multiplier block to obtain a set of partial product results. The partial product results are sent to a carry-save adder block. A partial product reduction is performed on the partial product results to generate a carry-save result having a sum term and a carry term. The carry-save result is then formatted to generate a carry-out bit. The carry-save result is added to a third operand to generate a final result.

Fused multiply add pipeline

A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.

Handling denormal floating point operands when result must be normalized

A floating point processor unit includes a shift amount calculation circuit within a normalizer portion of the floating point unit, wherein the shift amount calculation circuit is utilized to compute the normalizer shift amount for a log estimate instruction that runs as a pipelinable instruction.

Normalizer shift prediction for log estimate instructions

A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC&#x2212;expB+CV).

Common shift-amount calculation for binary and hex floating point

The invention proposes a Floating Point Unit () with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic () which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic () which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic () which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic () which adds the outputs of the alignment logic () and the multiply logic (), with a normalization logic () which normalizes the output of the adder logic (), which is characterized in that a leading zero logic () is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic () is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic () output have all the same value in order to: a) control the carry logic of the adder logic () and/or b) control a stage of the normalization logic ().

Floating point unit with fused multiply add and method for calculating a result with a floating point unit

A method for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.

In a system for conducting virtual address translation in a virtual memory system and implementing a table such as a Translation Lookaside Buffer, a system and method enabling quicker access to tables entries in which the entries are addressed after adding a plurality of address parts wherein the plurality is two (2) or (3). Particularly, a smaller and/or faster adder is used having, for example, only n&equals;2 ports in the time critical path. In order to make the exact address calculation, during array accesses, a multiplexor is implemented to decide, after the TLB arrays are accessed for preselection, which of a plurality of possible entries has to be taken.

Method and system for fast access to a translation lookaside buffer

The integration of multiple application programs on one chip card is described, whereby the application programs stored on it do not have access to each other, which is achieved through a separation and de-coupling of the individual programs from one another. A first embodiment has several mutually-independent units, consisting respectively of a processor unit and a memory unit. Communication of these independent units with the external world and also with each other takes place through a control unit. A communication of the independent units with each other can only take place through the respective processor units, so that the linked memory units may not be accessed by circumvention of the processor unit. In a further embodiment, the separation of different applications on a chip card with only one processor takes place through the insertion of a separation of the application segments in the memory area of the chip card. The separation has as a result that each application may only access one predetermined area within the memory, and that access outside of the specified memory area is disabled for this application.

Multiple application chip card with decoupled programs

Carry-select adder with pre-counting of leading zero digits

A digital circuit computes the logarithm of a number. The circuit makes the computation by first determining a multiplicity of factors f.sub.i from a predetermined set of factors such that the product of the multiplicity of factors f.sub.i and the number equals the base of the logarithm. A memory stores the logarithms of all the numbers in the predetermined set. The circuit then looks-up and sums the logarithms of the multiplicity of factors f.sub.i, and then subtracts the sum from one to yield the logarithm of the number.

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Stuttgart, Germany

Son Dao Trong