Texas Instruments Corporation

Solexel, Inc.

Applied Materials, Inc.

Novellus Systems Incorporated

Crystal Solar, Inc.

Aixtron Se

Ob Realty, LLC

Somnath S Nag

Mehrdad M Moslehi

Amitava Chatterjee

George D Kamian

Karl-Josef Kramer

Takao Yonehara

David Xuan-Qi Wang

Pawan Kapur

Girish Anant Dixit

Ajit P Paranjpe

Ih-Chin Chen

Kramadhati V Ravi

Suketu Arun Parikh

Tirunelveli Subramaniam Ravi

Subramanian Tamilmani

Jay Ashjaee

David Dutton

Ashish Asthana

Nevran Ozguven

Joe Kramer

Sanjeev Jain

Theodore Warren Houston

Bart Jan Van Schravendijk

Wei-Yung Hsu

Jengyi Yu

Haiying Fu

Guoqiang Xing

Keith Alan Joyner

M Ziaul Karim

Srikanth Krishnan

Maxim Kelman

Changming Jin

Jeffrey A McKee

Gregory Boyd Shinn

Richard Scott List

Robert A Ditizio

Yin Hu

Peter S McAnally

Iqbal Ali

Atul Gupta

Ka Shun Wong

Gerrit J Kooi

Kenneth P MacWilliams

Burcu Ucok

Subbu Tamilmani

Doug Crafts

Benjamin P Shieh

Asli Buccu Ucok

Agerico L Esquirel

Zhongyuan Jia

Robert Ditizio

Described herein are techniques for forming an epitaxial III-V layer on a substrate. In a pre-clean chamber, a native oxygen layer may be replaced with a passivation layer by treating the substrate with a hydrogen plasma (or products of a plasma decomposition). In a deposition chamber, the temperature of the substrate may be elevated to a temperature less than 700&#xb0; C. While the substrate temperature is elevated, a group V precursor may be flowed into the deposition chamber in order to transform the hydrogen terminated (Si&#x2014;H) surface of the passivation layer into an Arsenic terminated (Si&#x2014;As) surface. After the substrate has been cooled, a group III precursor and the group V precursor may be flowed in order to form a nucleation layer. Finally, at an elevated temperature, the group III precursor and group V precursor may be flowed in order to form a bulk III-V layer.

Formation of a layer on a semiconductor substrate

This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further the disclosure is applicable to the general fields of Photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

High-productivity porous semiconductor manufacturing equipment

Methods of fabricating metal wrap through solar cells and modules for thin silicon solar cells, including epitaxial silicon solar cells, are described. These metal wrap through solar cells have a planar back contact geometry for the base and emitter contacts. Fabrication of a metal wrap through solar cell may comprise: providing a photovoltaic device attached at the emitter side of the device to a solar glass by an encapsulant, the device including busbars on the device emitter; forming vias through the device base and emitter, the vias terminating in the busbars; depositing a conformal dielectric film over the surface of the vias and the back surface of the base; removing portions of the conformal dielectric film from the ends of the vias for exposing the busbars and from field areas of the base; and forming separate electrical contacts to the busbars and the field areas on the back surface of the solar cell. The solar cells may comprise epitaxially deposited silicon and may include an epitaxially deposited back surface field.

Method of fabricating a metal wrap through solar cell

An apparatus for forming porous silicon layers on at least two surfaces of a plurality of silicon templates in a batch electrochemical anodic etch process is provided. The apparatus comprises a plurality of edge-sealing template mounts operable to prevent formation of porous silicon at the edges of a plurality of templates. An electrolyte is disposed among the plurality of templates. The apparatus further comprises a power supply operable to switch polarity, change current intensity, and control etching time to produce the porous silicon layers.

Apparatus for forming porous silicon layers on at least two surfaces of a plurality of silicon templates

Methods here disclosed provide for selectively coating three-dimensional features on a substrate while avoiding liquid coating material wicking into micro cavities on the substrates. The steps include depositing a semiconductor layer on a sacrificial layer formed on a template and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating three-dimensional features on the substrate using a liquid coating step for applying a liquid coating material to a pre-determined surface of the three-dimensional features on the substrate.

Methods for selectively coating three-dimensional features on a substrate

A structure and method operable to create a reusable template for detachable thin semiconductor substrates is provided. The reusable template has a three-dimensional (3-D) surface topography comprising a plurality of raised areas comprising a rounded top and separated by a plurality of depressed areas.

Structure and method for creating a reusable template for detachable thin film substrates

It is an object of this disclosure to provide high productivity, low cost-of-ownership manufacturing equipment for the high volume production of photovoltaic (PV) solar cell device architecture. It is a further object of this disclosure to reduce material processing steps and material cost compared to existing technologies by using gas-phase source silicon. The present disclosure teaches the fabrication of a sacrificial substrate base layer that is compatible with a gas-phase substrate growth process. Porous silicon is used as the sacrificial layer in the present disclosure. Further, the present disclosure provides equipment to produce a sacrificial porous silicon PV cell-substrate base layer.

Porous silicon electro-etching system and method

MWT architecture for thin SI solar cells

Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate. Additional features may include filling the micro cavities of the substrate with a filling material, removing the filling material to expose only the substrate surfaces to be coated, coating the substrate with a layer of liquid coating material, and removing said filling material from the micro cavities of the substrate.

Methods for liquid transfer coating of three-dimensional substrates

A structure and method operable to create a reusable template for detachable thin semiconductor substrates is provided. The template has a shape such that the 3-D shape is substantially retained after each substrate release. Prior art reusable templates may have a tendency to change shape after each subsequent reuse; the present disclosure aims to address this and other deficiencies from the prior art, therefore increasing the reuse life of the template.

Method of creating reusable template for detachable thin film substrate

This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.

Double-sided reusable template for fabrication of semiconductor substrates for photovoltaic cell and microelectronics device manufacturing

A Schottky contact photovoltaic energy conversion cell. The Schottky contact photovoltaic energy conversion cell comprises a flexible substrate and a first array of a plurality of closely-spaced microscale pillars connected to a first electrical cell contact. The pillars and the contact are formed of (or having a top) layer of a first Schottky metal material with a work function selected for efficiently collecting photogenerated electrons. The Schottky contact photovoltaic energy conversion cell further comprises a second array of a plurality of closely-spaced microscale pillars connected to a second electrical cell contact. The pillars and the contact are formed of (or having a top) layer of a second Schottky metal material with a work function selected for efficiently collecting photogenerated holes. The Schottky contact photovoltaic energy conversion cell further comprises a semiconductor absorber thin-film layer covering the first and second contacts and filling spaces among all the pillars, for creating photogenerated electrons and holes.

High efficiency solar cells and manufacturing methods

A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Process sequence for doped silicon fill of deep trenches

A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Growing community of inventors

Plano, TX, United States of America

Somnath S Nag