Cypress Semiconductor Corporation

Cavium, Inc.

Somnath Paul

S Babar Raza

Jay Kishora Gupta

Hamid Khodabandehlou

Gregory H Efland

Amitabha Banerjee

Sanjay Rekhi

Paul H Scott

Bruce Anthony Klemin

Jason Baumbach

Rakesh Mehrotra

Gopal K Garg

Jiann-Cheng Chen

Muralidhar Jammula

Methods and systems for securing data are provided. For example, one method includes providing context information for an input/output (I/O) operation to a security module by an adapter communicating with a computing device and a storage device via a network; storing encryption parameters associated to a security association handle by the security module; using a workflow handle by the security module to obtain the security association handle for retrieving stored encryption parameters for encrypting payload transmitted by the adapter and for decrypting payload received by the adapter; predicting a first frame header for encrypting the payload transmitted by the adapter and a second frame header for decrypting payload received by the adapter; providing the encrypted payload for transmission to the adapter by the security module, after discarding the first predicted header; and providing the decrypted payload to the computing device by the security module, after discarding the second predicted header.

Methods and systems for securing data stored at a storage area network

A network interface to transport a continuous datastream over a frame-based transport network. The network interface includes a data input, an egress buffer circuit, a phase locked loop, and a data output. The data input receives frames carrying the continuous datastream from the frame-based transport network. The egress buffer circuit is coupled to buffer the continuous datastream and to generate a feedback signal based at least in part on a fill-level of the egress buffer. The phase locked loop is coupled to receive the feedback signal from the egress buffer and to recover a clock signal from the continuous datastream. The data output is coupled to output the data of the continuous datastream from the egress buffer circuit based on the clock signal.

Transmission of a continuous datastream through a re-clocked frame-based transport network

A system () can update a network performance counter and include link layer (MAC blocks) devices (-to-N) coupled in a daisy chain manner. A single performance counter () can serve all of the link layer devices (-to-N), receiving statistics vectors from all link layer devices (-to-N) and a vector enable signal from a last link layer device-N in the chain. A method () for updating a performance counter according to such a daisy chain configuration is also disclosed.

Method and apparatus for collecting statistical information from a plurality of packet processing blocks

A packet processing system including an encapsulator engine, and a packet pre-processor coupled to the encapsulator engine. The packet pre-processor calculates a variation between an input data rate and a pre-determined output data rate. The input data rate is based on a number of data read requests. The packet pre-processor compensates for the variation by modifying the number of data read requests.

Method of maximizing bandwidth efficiency in a protocol processor

Disclosed is an apparatus and method for an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments. The apparatus may include a data extraction block, a plurality of data assemblers, a scheduler, and an output memory. The scheduler may be configured to operate according to a scheduling policy. The scheduling policy may include a set of priorities to determine an order of scheduling writes to the output memory from a plurality of data assemblers. The scheduling policy may also include selecting one or more of the plurality of data assemblers having a fill level greater than twice an input data path width of an input data bus and having no end-of-packet (EOP) or start-of-packet (SOP) as a first priority, selecting one or more of the plurality of data assemblers having a fill level greater than twice the input data path width of the input data bus, and not covered in the first priority selection, as a second priority, selecting one or more of the plurality of data assemblers having a fill level greater than the input data path width of the input data bus, and not covered in the first and second priority selections, as a third priority, and selecting one or more of the plurality of data assemblers having an end-of-packet (EOP) as a fourth priority.

Scheduling store-forwarding of back-to-back multi-channel packet fragments

A method and apparatus for performing byte rate adaptation. Specifically, embodiments of the present invention describe a method for deleting bytes when performing byte rate adaptation. The method begins by receiving data at a first rate. The data comprises valid data and deletable data. The data also comprises a plurality of cycles, wherein each cycle comprises a word length of W bytes. The method continues by compressing the plurality of cycles into a compressed cycle by deleting redundant deletable bytes. The compressed cycle comprises at least one valid data byte. Thereafter, the method substitutes remaining deletable bytes in the first compressed cycle with a uniform character, and sends the compressed cycle to a FIFO buffer for further transmission.

Method and apparatus for the deletion of bytes when performing byte rate adaptation

Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read, and a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write.

First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access

Systems and methods for performing encoding and/or decoding can include an input data path that receives multiple input data values having an order (significance) with respect to one another. Each input data value can be applied to multiple compute paths (-to-N), each of which can precompute multiple output values based on a different predetermined disparity value. Multiplexers (-to-N) can output one precomputed output value according to a disparity value corresponding to a previous input data value in the order.

Multiple byte data path encoding/decoding device and method

A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment. The method also includes outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment. The method further includes selectively copying the double width image of the rotated data fragment from the bus to a location logically following the prior data fragment in a destination register.

Method and apparatus for assembling non-aligned packet fragments over multiple cycles

A method for multi-bit de-skewing of parallel bus signals is disclosed. The method includes receiving data comprising a multi-bit word and a training pattern. After a first control word of the training pattern is detected, the number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of a parallel bus is calculated. The number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of the parallel bus is transmitted to a bit delay line. The system then outputs a de-skewed data word.

Multi-bit deskewing of bus signals using a training pattern

An apparatus configured to extract in-band information or skip extraction of the in-band information and perform a look ahead operation. The apparatus may be configured to switch between the extraction and the skipping of the extraction.

Logic for generating multicast/unicast address (es)

In one embodiment, the invention is an apparatus. The apparatus includes a FIFO array having a first plurality of memory elements, each memory element having a predetermined number of bits, the FIFO array having a read pointer. The apparatus also includes a FIFO control register array having a second plurality of memory elements, each memory element of the second plurality corresponding to a memory element of the first plurality of memory elements, the read pointer suitable for accessing the FIFO control register array. The apparatus further includes a control logic block coupled to the FIFO control register array and the FIFO array. The control logic block is to receive a data value of the memory element of the FIFO control register array pointed to by the read pointer. The control logic block is also to signal the read pointer to stall responsive to the data value having a first value.

Method and apparatus for re-accessing a FIFO location

A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.

FIFO memory system and method

A circuit configured to provide a storage device comprising one or more virtual multiqueue FIFOs. The circuit is generally configured to operate at a preferred clock speed of a plurality of clock speeds.

Architecture for implementing virtual multiqueue fifos

An apparatus comprising a first logic circuit and a second logic circuit. The first logic circuit may comprise one or more counters and may be configured to synchronize a plurality of input clock signals. The second logic circuit may be configured to detect and present a faster clock signal of the synchronized clock signals.

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Milpitas, CA, United States of America

Somnath Paul