Intel Corporation

Somnath Ghosh

Rakesh Krishnaiyer

Wei Ey Li

Abhay Kanhere

Michael Apodaca

Dattatraya Kulkarni

David M Cimini

Thomas F Raoux

John Ng

Pratik J Ashar

Chu-Cheow Lim

Uddipan Mukherjee

Debraj Bose

Sthiti Deka

Yohai Gevim

Methods and apparatus relating to reducing memory latency in graphics operations are described. In an embodiment, uniform data is transferred from a buffer to a General Register File (GRF) of a processor based at least in part on information stored in a gather table. The uniform data comprises data that is uniform across a plurality of primitives in a graphics operation. Other embodiments are also disclosed and claimed.

Reducing memory latency in graphics operations

Vector processing systems and methods disclosed herein generate efficient vector initialization code that leverages performance advantages of single instruction, multiple data (SIMD) instructions and immediate operands. In some embodiments, a vector processing system scans existing code for initialization syntax that specifies values which match one or more target patterns. Where the vector processing system identifies one or more of these target patterns within the specified values, the vector processing system generates enhanced vector initialization code. This enhanced vector initialization code is configured to outperform vector initialization code that sequentially loads discrete values to discrete channels within a vector register.

Vector processing system

The prefetch distance to be used by a prefetch instruction may not always be correctly calculated using compile-time information. In one embodiment, the present invention generates prefetch distance calculation code to dynamically calculate a prefetch distance used by a prefetch instruction at run-time.

Dynamic prefetch distance calculation

An apparatus, method, and program product for optimizing code that contains dynamically-allocated memory. The aliasing behavior of internal pointers of dynamically-allocated memory is used to disambiguate memory accesses and to eliminate false data dependencies. It is determined whether a dynamically-allocated array will behave like a statically-allocated array throughout the entire program execution once it has been allocated. This determination is used to improve the instruction scheduling efficiency, which yields better performance.

Alias-free test for dynamic array structures

In general, the malloc-combining transformation optimization during compile-time of a source program engaged in dynamically constructing multi-dimensional arrays provides an effective method of improving cache locality by combining qualified malloc and free/realloc calls found in counted loops into a single system call and hoisting out the single call and placing it immediately preceding the beginning of the counted loops. As a result of the application of the malloc-combining optimization results in improved cache locality allows for prefetching array pointers and data elements of the dynamic arrays as if the dynamic arrays were static.

Compile-time memory coalescing for dynamic arrays

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San Jose, CA, United States of America

Somnath Ghosh