International Business Machines Corporation

Globalfoundries Inc.

Somnath Ghosh

Lawrence Alfred Clevenger

Robert Russell Robison

Hsueh-Chung Chen

Koichi Motoyama

Daniel James Dechene

Nicholas Anthony Lanzillo

Christopher J Penny

Timothy Mathew Philip

Ruilong Xie

Junli Wang

Dechao Guo

Kisik Choi

John Christopher Arnold

Chih-Chao Yang

Devendra K Sadana

Brent A Anderson

Carl John Radens

Chen Zhang

Chanro Park

Ekmini Anuja De Silva

Terry Allen Spooner

Nicholas V Licausi

Ravi Prakash Srivastava

Kenneth Chun Kuen Cheng

Dominik Metzler

Sagarika Mukesh

Sung Dae Suk

Devika Sarkar Grant

Sean Reidy

Qanit Takmeel

Alexander Reznicek

Balasubramanian Pranatharthiharan

Yann Mignot

Chi-Chun Liu

Huiming Bu

Albert Manhee Chu

Stuart A Sieg

Yongan Xu

Rishikesh Krishnan

David S Wolpert

Luke G England

Sunil Kumar Singh

Albert M Young

Karen Elizabeth Petrillo

Ming He

Kai Zhao

Craig Child

Daniel P Smith

Prakash Periasamy

Keith Donegan

Sukeshwar Kannan

Cody John Murray

Eswar Ramanathan

Michael Romain

Anbu Selvam Km Mahalingam

Anbu Selvam K M Mahalingam

Ashwini Chandrashekar

Colin Bombardier

Jeric Sarad

A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

Metal lines with low via-to-via spacing

Embodiments herein include semiconductor structures with a first source/drain (S/D) connected to a first field-effect transistor (FET) region, a second S/D connected to a second FET region, and a buried power rail (BPR) region. The BPR region may include a BPR, a first dielectric liner lining a first lateral side of the BPR region, and a second dielectric liner lining a second lateral side. The first dielectric liner isolates the BPR from the first FET region and the first S/D, and the second dielectric liner isolates the BPR from the second FET region. Embodiments may also include a contact electrically connecting the second S/D and the BPR through a second lateral side of the BPR region. The liners enable the BPR to be formed after the formation of gates and the S/Ds, so that the BPR does not cause problems during annealing processes of the gates and the S/Ds.

Buried power rail after replacement metal gate

A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Backside power rails and power distribution network for density scaling

A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

Three-dimensional, monolithically stacked field effect transistors formed on the front and backside of a wafer

Structures in semiconductor devices, and methods for forming the structures, are described. In one embodiment, a hard mask layer of a deposition stack can be etched to pattern a hard mask. An interconnect layer of the deposition stack can be etched using the hard mask to pattern a plurality of metal lines. The hard mask can be removed. A liner layer of the deposition stack can be etched to remove a portion of the liner layer deposited directly on a dielectric layer of the deposition stack. In response to etching the liner layer, a remaining portion of the liner layer can be deposited between the metal lines and the dielectric layer.

Selective metal residue and liner cleanse for post-subtractive etch

A method of making a back-end-of-line (BEOL) component includes filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material. The method further includes forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material. The method further includes removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material. The method further includes recessing the layer of metal material where the top surface of the layer of metal material is exposed. The method further includes removing the scaffolding material.

Subtractive patterning of interconnect structures

Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.

Buried power rails located in a base layer including first, second, and third etch stop layers

A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

Fully aligned top vias

A method can include obtaining characteristic data for a wafer. The characteristic data can correspond to the wafer in a processed state and can include a set of stress values of the wafer. The wafer can include a front side, a back side opposite the front side, and a set of regions. The set of stress values can include a first stress value corresponding to a first region. In the processed state, one or more front-side processes can be completed on the front side of the wafer. The method can include determining that the first stress value exceeds a stress threshold and generating a compensation map. The compensation map can identify one or more regions for forming one or more trenches. The method can include initiating, based on the compensation map, a formation of a first trench on the back side of the wafer in the first region.

Back-side wafer modification

A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.

Spin on scaffold film for forming topvia

An interlayer interconnect for an integrated circuit includes a first line in a first wiring layer, a first via portion integral to and extending from the first line, and a second line in a second wiring layer that is adjacent to the first wiring layer. The interlayer interconnect also includes a third line in the second wiring layer that is a first distance from the second line, wherein the first distance is a pitch of the second wiring layer, and a second via portion integral to and extending from the second line and in electrical contact with the first via portion at an interface to form a via. The via extends a second distance that is at least one-and-a-quarter times the pitch.

High aspect ratio vias for integrated circuits

A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.

Line cut patterning using sacrificial material

The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.

Metal on metal multiple patterning

A method includes applying a first metallic layer having a first metallic material onto a substrate of a semiconductor component. The method further includes removing portions of the first metallic layer to form a first metallic line. The method further includes creating an opening in the first metallic line. The method also includes depositing a dielectric material on the substrate. The method further includes forming at least one trench in the dielectric material. The method also includes depositing a second metallic material within the at least one trench to form a second metallic line. At least the first and second metallic lines and the dielectric material form an interconnect structure of the semiconductor component.

Cut integration for subtractive first metal line with bottom up second metal line

Growing community of inventors

Clifton Park, NY, United States of America

Somnath Ghosh